How to convert this simulink model to VHDL ?

I have simulated a sinusoidal wave using the SIMULINK by using an integrator,gain and constant. I tried to convert this to VHDL but not able to do so.

This is the SIMULINK model which I simulated in SIMULINK which I got a sinusoidal output. I want to know what are the necessary changes which I have to do in order to get a VHDL code for the same?

[Nitin Kapgate]

Which tool you are using for Simulink model to VHDL code transformation? HDL Coder?

[Jerry Jacob]

Well I am using the VHDL coder and converted the above simulink model to the discrete form for conversion.

I have converted them to VHDL and tried running this on ModelSim. On running this for the same, I got the following error.

Fatal Error in in Process Out1_expected_fileread at D:/intelFPGA/logs/Subsystem_tb.vhd line 243

The above error is found in the TestBench.

These are the VHDL code, testbench and package that was generated via the HDL generator.

Kindly look into these and tell me what can I do ?

The Testbench

-- -------------------------------------------------------------
-- 
-- File Name: hdl_prj\hdlsrc\oscillator\Subsystem_tb.vhd
-- Created: 2021-01-13 09:14:47
-- 
-- Generated by MATLAB 9.6 and HDL Coder 3.14
-- 
-- 
-- -------------------------------------------------------------
-- Rate and Clocking Details
-- -------------------------------------------------------------
-- Model base rate: 0.01
-- Target subsystem base rate: 0.01
-- 
-- 
-- Clock Enable  Sample Time
-- -------------------------------------------------------------
-- ce_out        0.01
-- -------------------------------------------------------------
-- 
-- 
-- Output Signal                 Clock Enable  Sample Time
-- -------------------------------------------------------------
-- Out1                          ce_out        0.01
-- -------------------------------------------------------------
-- 
-- -------------------------------------------------------------


-- -------------------------------------------------------------
-- 
-- Module: Subsystem_tb
-- Source Path: 
-- Hierarchy Level: 0
-- 
-- -------------------------------------------------------------
LIBRARY IEEE;
USE IEEE.std_logic_textio.ALL;
USE IEEE.float_pkg.ALL;
USE IEEE.std_logic_1164.ALL;
USE IEEE.numeric_std.ALL;
--LIBRARY STD;
use std.textio.all;
USE work.Subsystem_tb_pkg.ALL;

ENTITY Subsystem_tb IS
END Subsystem_tb;


ARCHITECTURE rtl OF Subsystem_tb IS

  ATTRIBUTE multstyle : string;

  -- Component Declarations
  COMPONENT Subsystem
    PORT( clk                             :   IN    std_logic;
          reset                           :   IN    std_logic;
          clk_enable                      :   IN    std_logic;
          In1                             :   IN    std_logic_vector(15 DOWNTO 0);  -- sfix16_En13
          ce_out                          :   OUT   std_logic;
          Out1                            :   OUT   std_logic_vector(15 DOWNTO 0)  -- sfix16_En13
          );
  END COMPONENT;

  -- Component Configuration Statements
  FOR ALL : Subsystem
    USE ENTITY work.Subsystem(rtl);

  -- Signals
  SIGNAL clk                              : std_logic;
  SIGNAL reset                            : std_logic;
  SIGNAL clk_enable                       : std_logic;
  SIGNAL rawData_In1                      : signed(15 DOWNTO 0);  -- sfix16_En13
  SIGNAL Out1_done                        : std_logic;  -- ufix1
  SIGNAL rdEnb                            : std_logic;
  SIGNAL Out1_done_enb                    : std_logic;  -- ufix1
  SIGNAL Out1_addr                        : unsigned(13 DOWNTO 0);  -- ufix14
  SIGNAL Out1_active                      : std_logic;  -- ufix1
  SIGNAL holdData_In1                     : signed(15 DOWNTO 0);  -- sfix16_En13
  SIGNAL In1_offset                       : signed(15 DOWNTO 0);  -- sfix16_En13
  SIGNAL In1_1                            : signed(15 DOWNTO 0);  -- sfix16_En13
  SIGNAL In1_2                            : std_logic_vector(15 DOWNTO 0);  -- ufix16
  SIGNAL check1_done                      : std_logic;  -- ufix1
  SIGNAL snkDonen                         : std_logic;
  SIGNAL resetn                           : std_logic;
  SIGNAL tb_enb                           : std_logic;
  SIGNAL tb_enb_delay                     : std_logic;
  SIGNAL ce_out                           : std_logic;
  SIGNAL Out1                             : std_logic_vector(15 DOWNTO 0);  -- ufix16
  SIGNAL Out1_enb                         : std_logic;  -- ufix1
  SIGNAL Out1_lastAddr                    : std_logic;  -- ufix1
  SIGNAL Out1_signed                      : signed(15 DOWNTO 0);  -- sfix16_En13
  SIGNAL Out1_addr_delay_1                : unsigned(13 DOWNTO 0);  -- ufix14
  SIGNAL Out1_expected                    : signed(15 DOWNTO 0);  -- sfix16_En13
  SIGNAL Out1_ref                         : signed(15 DOWNTO 0);  -- sfix16_En13
  SIGNAL Out1_testFailure                 : std_logic;  -- ufix1

BEGIN
  u_Subsystem : Subsystem
    PORT MAP( clk => clk,
              reset => reset,
              clk_enable => clk_enable,
              In1 => In1_2,  -- sfix16_En13
              ce_out => ce_out,
              Out1 => Out1  -- sfix16_En13
              );

  -- Data source for In1
  rawData_In1 <= to_signed(16#2000#, 16);

  Out1_done_enb <= Out1_done AND rdEnb;

  
  Out1_active <= '1' WHEN Out1_addr /= to_unsigned(16#2710#, 14) ELSE
      '0';

  -- holdData reg for Constant_out1
  stimuli_Constant_out1_process: PROCESS (clk)
  BEGIN
    IF clk'event AND clk = '1' THEN
      IF reset = '1' THEN
        holdData_In1 <= (OTHERS => 'X');
      ELSE
        holdData_In1 <= rawData_In1;
      END IF;
    END IF;
  END PROCESS stimuli_Constant_out1_process;

  stimuli_Constant_out1_1: PROCESS (rawData_In1, rdEnb)
  BEGIN
    IF rdEnb = '0' THEN
      In1_offset <= holdData_In1;
    ELSE
      In1_offset <= rawData_In1;
    END IF;
  END PROCESS stimuli_Constant_out1_1;

  In1_1 <= In1_offset AFTER 2 ns;

  In1_2 <= std_logic_vector(In1_1);

  snkDonen <=  NOT check1_done;

  resetn <=  NOT reset;

  tb_enb <= resetn AND snkDonen;

  -- Delay inside enable generation: register depth 1
  u_enable_delay_process: PROCESS (clk)
  BEGIN
    IF clk'event AND clk = '1' THEN
      IF reset = '1' THEN
        tb_enb_delay <= '0';
      ELSE
        tb_enb_delay <= tb_enb;
      END IF;
    END IF;
  END PROCESS u_enable_delay_process;

  
  rdEnb <= tb_enb_delay WHEN check1_done = '0' ELSE
      '0';

  clk_enable <= rdEnb AFTER 2 ns;

  reset_gen: PROCESS 
  BEGIN
    reset <= '1';
    WAIT FOR 20 ns;
    WAIT UNTIL clk'event AND clk = '1';
    WAIT FOR 2 ns;
    reset <= '0';
    WAIT;
  END PROCESS reset_gen;

  clk_gen: PROCESS 
  BEGIN
    clk <= '1';
    WAIT FOR 5 ns;
    clk <= '0';
    WAIT FOR 5 ns;
    IF check1_done = '1' THEN
      clk <= '1';
      WAIT FOR 5 ns;
      clk <= '0';
      WAIT FOR 5 ns;
      WAIT;
    END IF;
  END PROCESS clk_gen;

  Out1_enb <= ce_out AND Out1_active;

  -- Count limited, Unsigned Counter
  --  initial value   = 0
  --  step value      = 1
  --  count to value  = 10000
  c_3_process : PROCESS (clk)
  BEGIN
    IF clk'EVENT AND clk = '1' THEN
      IF reset = '1' THEN
        Out1_addr <= to_unsigned(16#0000#, 14);
      ELSIF Out1_enb = '1' THEN
        IF Out1_addr >= to_unsigned(16#2710#, 14) THEN 
          Out1_addr <= to_unsigned(16#0000#, 14);
        ELSE 
          Out1_addr <= Out1_addr + to_unsigned(16#0001#, 14);
        END IF;
      END IF;
    END IF;
  END PROCESS c_3_process;


  
  Out1_lastAddr <= '1' WHEN Out1_addr >= to_unsigned(16#2710#, 14) ELSE
      '0';

  Out1_done <= Out1_lastAddr AND resetn;

  -- Delay to allow last sim cycle to complete
  checkDone_1_process: PROCESS (clk)
  BEGIN
    IF clk'event AND clk = '1' THEN
      IF reset = '1' THEN
        check1_done <= '0';
      ELSIF Out1_done_enb = '1' THEN
        check1_done <= Out1_done;
      END IF;
    END IF;
  END PROCESS checkDone_1_process;

  Out1_signed <= signed(Out1);

  Out1_addr_delay_1 <= Out1_addr AFTER 1 ns;

  -- Data source for Out1_expected
  Out1_expected_fileread: PROCESS (Out1_addr_delay_1, tb_enb_delay, ce_out);
  FILE fp: TEXT open READ_MODE is "Out1_expected.dat";
    VARIABLE l: LINE;
    VARIABLE read_data: std_logic_vector(15 DOWNTO 0);

  BEGIN
    IF tb_enb_delay /= '1' THEN
    ELSIF ce_out = '1' AND NOT ENDFILE(fp) THEN
      READLINE(fp, l);
      HREAD(l, read_data);
    END IF;
    Out1_expected <= signed(read_data(15 DOWNTO 0));
  END PROCESS Out1_expected_fileread;

  Out1_ref <= Out1_expected;

  Out1_signed_checker: PROCESS (clk, reset)
  BEGIN
    IF reset = '1' THEN
      Out1_testFailure <= '0';
    ELSIF clk'event AND clk = '1' THEN
      IF ce_out = '1' AND Out1_signed /= Out1_ref THEN
        Out1_testFailure <= '1';
        ASSERT FALSE
          REPORT "Error in Out1_signed: Expected " & to_hex(Out1_ref) & (" Actual " & to_hex(Out1_signed))
          SEVERITY ERROR;
      END IF;
    END IF;
  END PROCESS Out1_signed_checker;

  completed_msg: PROCESS (clk)
  BEGIN
    IF clk'event AND clk = '1' THEN
      IF check1_done = '1' THEN
        IF Out1_testFailure = '0' THEN
          ASSERT FALSE
            REPORT "**************TEST COMPLETED (PASSED)**************"
            SEVERITY NOTE;
        ELSE
          ASSERT FALSE
            REPORT "**************TEST COMPLETED (FAILED)**************"
            SEVERITY NOTE;
        END IF;
      END IF;
    END IF;
  END PROCESS completed_msg;

END rtl;

The package

-- -------------------------------------------------------------
-- 
-- File Name: hdl_prj\hdlsrc\oscillator\Subsystem_tb_pkg.vhd
-- Created: 2021-01-13 09:14:47
-- 
-- Generated by MATLAB 9.6 and HDL Coder 3.14
-- 
-- -------------------------------------------------------------


LIBRARY IEEE;
USE IEEE.std_logic_1164.ALL;
USE IEEE.numeric_std.ALL;
LIBRARY IEEE;
USE IEEE.std_logic_textio.ALL;
USE IEEE.float_pkg.ALL;
--LIBRARY STD;
USE STD.textio.ALL;

PACKAGE Subsystem_tb_pkg IS
  -- Functions
  FUNCTION to_hex(x : IN std_logic) RETURN string;
  FUNCTION to_hex(x : IN std_logic_vector) RETURN string;
  FUNCTION to_hex(x : IN signed) RETURN string;
  FUNCTION to_hex(x : IN unsigned) RETURN string;
  FUNCTION to_hex(x : IN real) RETURN string;
END Subsystem_tb_pkg;


PACKAGE BODY Subsystem_tb_pkg IS
  FUNCTION to_hex(x : IN std_logic_vector) RETURN string IS
    VARIABLE result : STRING(1 TO 256);
    VARIABLE i      : INTEGER;
    VARIABLE imod   : INTEGER;
    VARIABLE j      : INTEGER;
    VARIABLE jinc   : INTEGER;
    VARIABLE newx   : std_logic_vector(1023 DOWNTO 0);
  BEGIN
    newx := (OTHERS => '0');
    IF x'LEFT > x'RIGHT THEN
      j := x'LENGTH - 1;
      jinc := -1;
    ELSE
      j := 0;
      jinc := 1;
    END IF;
    FOR i IN x'RANGE LOOP
      newx(j) := x(i);
      j := j + jinc;
    END LOOP;
    i := x'LENGTH - 1;
    imod := x'LENGTH MOD 4;
    IF    imod = 1 THEN i := i + 3;
    ELSIF imod = 2 THEN i := i + 2;
    ELSIF imod = 3 THEN i := i + 1;
    END IF;
    j := 1;
    WHILE i >= 3 LOOP
      IF    newx(i DOWNTO (i-3)) = "0000" THEN result(j) := '0';
      ELSIF newx(i DOWNTO (i-3)) = "0001" THEN result(j) := '1';
      ELSIF newx(i DOWNTO (i-3)) = "0010" THEN result(j) := '2';
      ELSIF newx(i DOWNTO (i-3)) = "0011" THEN result(j) := '3';
      ELSIF newx(i DOWNTO (i-3)) = "0100" THEN result(j) := '4';
      ELSIF newx(i DOWNTO (i-3)) = "0101" THEN result(j) := '5';
      ELSIF newx(i DOWNTO (i-3)) = "0110" THEN result(j) := '6';
      ELSIF newx(i DOWNTO (i-3)) = "0111" THEN result(j) := '7';
      ELSIF newx(i DOWNTO (i-3)) = "1000" THEN result(j) := '8';
      ELSIF newx(i DOWNTO (i-3)) = "1001" THEN result(j) := '9';
      ELSIF newx(i DOWNTO (i-3)) = "1010" THEN result(j) := 'A';
      ELSIF newx(i DOWNTO (i-3)) = "1011" THEN result(j) := 'B';
      ELSIF newx(i DOWNTO (i-3)) = "1100" THEN result(j) := 'C';
      ELSIF newx(i DOWNTO (i-3)) = "1101" THEN result(j) := 'D';
      ELSIF newx(i DOWNTO (i-3)) = "1110" THEN result(j) := 'E';
      ELSIF newx(i DOWNTO (i-3)) = "1111" THEN result(j) := 'F';
      ELSE result(j) := 'X';
      END IF;
      i := i - 4;
      j := j + 1;
    END LOOP;
    RETURN result(1 TO j - 1);
  END;

  FUNCTION to_hex(x : IN std_logic) RETURN string IS
  BEGIN
    RETURN std_logic'image(x);
  END;

  FUNCTION to_hex(x : IN signed) RETURN string IS
  BEGIN
    RETURN to_hex(std_logic_vector(x));
  END;

  FUNCTION to_hex(x : IN unsigned) RETURN string IS
  BEGIN
    RETURN to_hex(std_logic_vector(x));
  END;

  FUNCTION to_hex(x : IN real) RETURN string IS
  BEGIN
    RETURN real'image(x);
  END;

END Subsystem_tb_pkg;

The RTL program

-- -------------------------------------------------------------
-- 
-- File Name: hdl_prj\hdlsrc\oscillator\Subsystem.vhd
-- Created: 2021-01-13 09:20:53
-- 
-- Generated by MATLAB 9.6 and HDL Coder 3.14
-- 
-- 
-- -------------------------------------------------------------
-- Rate and Clocking Details
-- -------------------------------------------------------------
-- Model base rate: 0.01
-- Target subsystem base rate: 0.01
-- 
-- 
-- Clock Enable  Sample Time
-- -------------------------------------------------------------
-- ce_out        0.01
-- -------------------------------------------------------------
-- 
-- 
-- Output Signal                 Clock Enable  Sample Time
-- -------------------------------------------------------------
-- Out1                          ce_out        0.01
-- -------------------------------------------------------------
-- 
-- -------------------------------------------------------------


-- -------------------------------------------------------------
-- 
-- Module: Subsystem
-- Source Path: oscillator/Subsystem
-- Hierarchy Level: 0
-- 
-- -------------------------------------------------------------
LIBRARY IEEE;
USE IEEE.std_logic_1164.ALL;
USE IEEE.numeric_std.ALL;

ENTITY Subsystem IS
  PORT( clk                               :   IN    std_logic;
        reset                             :   IN    std_logic;
        clk_enable                        :   IN    std_logic;
        In1                               :   IN    std_logic_vector(15 DOWNTO 0);  -- sfix16_En13
        ce_out                            :   OUT   std_logic;
        Out1                              :   OUT   std_logic_vector(15 DOWNTO 0)  -- sfix16_En13
        );
END Subsystem;


ARCHITECTURE rtl OF Subsystem IS

  -- Signals
  SIGNAL enb                              : std_logic;
  SIGNAL Discrete_Time_Integrator_reg_ctrl_const_out : std_logic;
  SIGNAL Discrete_Time_Integrator_reg_ctrl_delay_out : std_logic;
  SIGNAL Discrete_Time_Integrator_reg_Initial_Val_out : signed(15 DOWNTO 0);  -- sfix16_En13
  SIGNAL In1_signed                       : signed(15 DOWNTO 0);  -- sfix16_En13
  SIGNAL Discrete_Time_Integrator1_reg_ctrl_const_out : std_logic;
  SIGNAL Discrete_Time_Integrator1_reg_ctrl_delay_out : std_logic;
  SIGNAL Discrete_Time_Integrator1_reg_Initial_Val_out : signed(15 DOWNTO 0);  -- sfix16_En13
  SIGNAL Discrete_Time_Integrator_u_add   : signed(15 DOWNTO 0);  -- sfix16_En13
  SIGNAL Product1_mul_temp                : signed(31 DOWNTO 0);  -- sfix32_En26
  SIGNAL Product1_out1                    : signed(15 DOWNTO 0);  -- sfix16_En13
  SIGNAL Discrete_Time_Integrator1_indtc  : signed(15 DOWNTO 0);  -- sfix16
  SIGNAL gain1_mul_temp                   : signed(31 DOWNTO 0);  -- sfix32_En19
  SIGNAL Discrete_Time_Integrator1_u_gain : signed(15 DOWNTO 0);  -- sfix16
  SIGNAL Discrete_Time_Integrator1_u_dtc  : signed(15 DOWNTO 0);  -- sfix16_En13
  SIGNAL Discrete_Time_Integrator1_out1   : signed(15 DOWNTO 0);  -- sfix16_En13
  SIGNAL Discrete_Time_Integrator1_x_reg  : signed(15 DOWNTO 0);  -- sfix16_En13
  SIGNAL Discrete_Time_Integrator1_u_add  : signed(15 DOWNTO 0);  -- sfix16_En13
  SIGNAL Gain_cast                        : signed(16 DOWNTO 0);  -- sfix17_En13
  SIGNAL Gain_cast_1                      : signed(16 DOWNTO 0);  -- sfix17_En13
  SIGNAL Gain_cast_2                      : signed(31 DOWNTO 0);  -- sfix32_En28
  SIGNAL Gain_out1                        : signed(15 DOWNTO 0);  -- sfix16_En13
  SIGNAL Product_mul_temp                 : signed(31 DOWNTO 0);  -- sfix32_En26
  SIGNAL Product_out1                     : signed(15 DOWNTO 0);  -- sfix16_En13
  SIGNAL Discrete_Time_Integrator_indtc   : signed(15 DOWNTO 0);  -- sfix16
  SIGNAL gain_mul_temp                    : signed(31 DOWNTO 0);  -- sfix32_En19
  SIGNAL Discrete_Time_Integrator_u_gain  : signed(15 DOWNTO 0);  -- sfix16
  SIGNAL Discrete_Time_Integrator_u_dtc   : signed(15 DOWNTO 0);  -- sfix16_En13
  SIGNAL Discrete_Time_Integrator_reg_out : signed(15 DOWNTO 0);  -- sfix16_En13
  SIGNAL Discrete_Time_Integrator_x_reg   : signed(15 DOWNTO 0);  -- sfix16_En13

  ATTRIBUTE multstyle : string;

BEGIN
  Discrete_Time_Integrator_reg_ctrl_const_out <= '1';

  enb <= clk_enable;

  Discrete_Time_Integrator_reg_ctrl_delay_process : PROCESS (clk)
  BEGIN
    IF clk'EVENT AND clk = '1' THEN
      IF reset = '1' THEN
        Discrete_Time_Integrator_reg_ctrl_delay_out <= '0';
      ELSIF enb = '1' THEN
        Discrete_Time_Integrator_reg_ctrl_delay_out <= Discrete_Time_Integrator_reg_ctrl_const_out;
      END IF;
    END IF;
  END PROCESS Discrete_Time_Integrator_reg_ctrl_delay_process;


  Discrete_Time_Integrator_reg_Initial_Val_out <= to_signed(16#4000#, 16);

  In1_signed <= signed(In1);

  Discrete_Time_Integrator1_reg_ctrl_const_out <= '1';

  Discrete_Time_Integrator1_reg_ctrl_delay_process : PROCESS (clk)
  BEGIN
    IF clk'EVENT AND clk = '1' THEN
      IF reset = '1' THEN
        Discrete_Time_Integrator1_reg_ctrl_delay_out <= '0';
      ELSIF enb = '1' THEN
        Discrete_Time_Integrator1_reg_ctrl_delay_out <= Discrete_Time_Integrator1_reg_ctrl_const_out;
      END IF;
    END IF;
  END PROCESS Discrete_Time_Integrator1_reg_ctrl_delay_process;


  Discrete_Time_Integrator1_reg_Initial_Val_out <= to_signed(16#2000#, 16);

  -- <S1>/Product1
  Product1_mul_temp <= In1_signed * Discrete_Time_Integrator_u_add;
  Product1_out1 <= Product1_mul_temp(28 DOWNTO 13);

  Discrete_Time_Integrator1_indtc <= Product1_out1;

  gain1_mul_temp <= to_signed(16#147B#, 16) * Discrete_Time_Integrator1_indtc;
  Discrete_Time_Integrator1_u_gain <= resize(gain1_mul_temp(31 DOWNTO 19), 16);

  Discrete_Time_Integrator1_u_dtc <= Discrete_Time_Integrator1_u_gain;

  
  Discrete_Time_Integrator1_x_reg <= Discrete_Time_Integrator1_reg_Initial_Val_out WHEN Discrete_Time_Integrator1_reg_ctrl_delay_out = '0' ELSE
      Discrete_Time_Integrator1_out1;

  Discrete_Time_Integrator1_u_add <= Discrete_Time_Integrator1_x_reg + Discrete_Time_Integrator1_u_dtc;

  -- <S1>/Discrete-Time Integrator1
  -- 
  -- <S1>/Delay
  reduced_process : PROCESS (clk)
  BEGIN
    IF clk'EVENT AND clk = '1' THEN
      IF reset = '1' THEN
        Discrete_Time_Integrator1_out1 <= to_signed(16#0000#, 16);
      ELSIF enb = '1' THEN
        Discrete_Time_Integrator1_out1 <= Discrete_Time_Integrator1_u_add;
      END IF;
    END IF;
  END PROCESS reduced_process;


  -- <S1>/Gain
  Gain_cast <= resize(Discrete_Time_Integrator1_out1, 17);
  Gain_cast_1 <=  - (Gain_cast);
  Gain_cast_2 <= Gain_cast_1 & '0' & '0' & '0' & '0' & '0' & '0' & '0' & '0' & '0' & '0' & '0' & '0' & '0' & '0' & '0';
  Gain_out1 <= Gain_cast_2(30 DOWNTO 15);

  -- <S1>/Product
  Product_mul_temp <= In1_signed * Gain_out1;
  Product_out1 <= Product_mul_temp(28 DOWNTO 13);

  Discrete_Time_Integrator_indtc <= Product_out1;

  gain_mul_temp <= to_signed(16#147B#, 16) * Discrete_Time_Integrator_indtc;
  Discrete_Time_Integrator_u_gain <= resize(gain_mul_temp(31 DOWNTO 19), 16);

  Discrete_Time_Integrator_u_dtc <= Discrete_Time_Integrator_u_gain;

  -- <S1>/Discrete-Time Integrator
  Discrete_Time_Integrator_reg_process : PROCESS (clk)
  BEGIN
    IF clk'EVENT AND clk = '1' THEN
      IF reset = '1' THEN
        Discrete_Time_Integrator_reg_out <= to_signed(16#0000#, 16);
      ELSIF enb = '1' THEN
        Discrete_Time_Integrator_reg_out <= Discrete_Time_Integrator_u_add;
      END IF;
    END IF;
  END PROCESS Discrete_Time_Integrator_reg_process;


  
  Discrete_Time_Integrator_x_reg <= Discrete_Time_Integrator_reg_Initial_Val_out WHEN Discrete_Time_Integrator_reg_ctrl_delay_out = '0' ELSE
      Discrete_Time_Integrator_reg_out;

  Discrete_Time_Integrator_u_add <= Discrete_Time_Integrator_x_reg + Discrete_Time_Integrator_u_dtc;

  Out1 <= std_logic_vector(Discrete_Time_Integrator_u_add);

  ce_out <= clk_enable;

END rtl;

Answer 1

[Kiran Kintali]

Attached a sample model. Please feel free to share your models.

1. What is the exact frequency and is it a constant or variable with some range?
2. Data type that is targeted fixed point or floating point?
3. Sample time for the waveforms?

[Jerry Jacob]

Well I have a model with a Fourier Series coefficients like this

x3=[-33.3204 -46.9692 0.0126 -4.8866 16.3788 0.0126 -1.2220 -6.4403 0.0126 -4.9632 -7.8041 0.0126 -4.9944 4.4077 0.0126 -1.4650 -1.7672 0.0126 -5.0854 -1.7187 0.0126 -5.1889 0.7203 0.0126 4.7573];

a03=x3(1); w3=x3(3);

a13=x3(2)*cos(x3(4)); b13=x3(2)*sin(x3(4));

a23=x3(5)*cos(x3(7)); b23=x3(5)*sin(x3(7));

a33=x3(8)*cos(x3(10)); b33=x3(8)*sin(x3(10));

a43=x3(11)*cos(x3(13)); b43=x3(11)*sin(x3(13));

a53=x3(14)*cos(x3(16)); b53=x3(14)*sin(x3(16));

a63=x3(17)*cos(x3(19)); b63=x3(17)*sin(x3(19));

a73=x3(20)*cos(x3(22)); b73=x3(20)*sin(x3(22));

a83=x3(23)*cos(x3(25)); b83=x3(23)*sin(x3(25));

The a13,......,a83 are the initial values of the first integrators and b13,......,b83 for the second one.The w is frequency in rad/sec. I used them creating multiple resonators and add them. How can I use it using your concept?? @Kiran Kintali

[Kiran Kintali]

Is this question related to HDL Code Generation? If yes, you need to partition the code into design and testbench modules.

[Jerry Jacob]

I want to create an overall oscillator with the above and find the sum of the entire resonator. So will the partition of code into design be possible? Is it possible to use a single clock ??