Set up HDL verifier

how can i fix this problem?
PS: I work with MATLAB 2019b, Quartus Prime 18.1 & FPGA cyclone IV GX.

Risposte (1)

YP
YP il 21 Nov 2022

0 voti

The command line window shows "Expected programming file not generated".
You may need to check the project log see why the bit file gen failed.

Richiesto:

il 16 Gen 2021

Risposto:

YP
il 21 Nov 2022

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