Display the RST port in a Xilinx FIL model
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I am generating a FPGA-in-the-Loop model using a Xilinx board. When you set the port types (DUT I/O Ports section in the FIL Wizard), you have to specify Clock, Clock Enable, and Reset signals. I can assign these fine, and they work with the generated FIL model; however, the CLK, CE, and RST ports are hidden when the FIL model is created - I would like to drive the RST signal with an input, and I am wondering how do I get the FIL model to generate with the RST port visible. I suppose I could create another Reset "Data" input and use that, but that seems like a kludge ... it seems like it should be an easy thing to do, but I can't figure it out. Any help would be appreciated!
Tao Jia on 19 Jul 2013
You'll have to create another "reset" signal as "data" port to use it in Simulink. FIL requires a dedicated reset signal so that we can make sure that the whole design is initialized properly at the beginning of simulation. It will only be asserted at the beginning of simulation. If you want to assert reset in the middle of simulation, you'll have to use another reset signal.
Hope this helps