QPSK Modulation Verilog Code generation error?
1 visualizzazione (ultimi 30 giorni)
Mostra commenti meno recenti
ali shan
il 4 Giu 2021
Risposto: Bharath Venkataraman
il 7 Giu 2021
Hello
hope you are doing well.
i am using QPSK modulation IP and want to create Verilog code using that but it show me some error like mention in picture![](https://www.mathworks.com/matlabcentral/answers/uploaded_files/642190/image.png)
![](https://www.mathworks.com/matlabcentral/answers/uploaded_files/642190/image.png)
0 Commenti
Risposta accettata
Bharath Venkataraman
il 7 Giu 2021
It appears that you need to covert the design to use fixed-point as well as set appropriate sample rates for your sources. Please take a look at this example to see how you can change your design.
0 Commenti
Più risposte (0)
Vedere anche
Community Treasure Hunt
Find the treasures in MATLAB Central and discover how the community can help you!
Start Hunting!