The function block "Integrate and Dump" (Simulink) is not supported for HDL code generation. Is there a similar one which is supported for HDL code generation? Thanks a lot!

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Hong Zhao
Hong Zhao il 9 Giu 2021
Commentato: Bharath Venkataraman il 16 Giu 2021
I am using HDL coder to convert my simlink design to VHDL code. There is an error generated saying "Integrate and Dump" is not supported for HDL code generation. I am wondering if there is a similar block to "Integrate and Dump" which is supported for HDL code generation. Thanks a lot!

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Bharath Venkataraman
Bharath Venkataraman il 14 Giu 2021
There isn't a direct single block substiture for the Integrate and Dump block, but the attached model shows the way you can model the behavior using more basic blocks.
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Hong Zhao
Hong Zhao il 16 Giu 2021
I have replaced delay3 with rate transition block and it worked out for my project perfectly. Thanks again!

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