Error in using rate transition for multiple clock domains

Hello.

I'm working on an SoC design that involves a single memory channel only (for I/O reasons) and storing four parallely processed image frames in that channel using an offset. For data coherency, I'm trying to implement different clock rates inside of the PL using rate transistion blocks. This is all nested in a subsystem called "FPGA". I'm getting this error when trying to do so though:

Port-based sample time block 'reimplementation_top/FPGA/Rate Transition' has a sample time, 2e-08 in an inheritable task, on 'Output Port 1' that does not align with the periodic sample time of the atomic subsystem 'reimplementation_top/FPGA'. Only constant (inf), inherited (-1), or periodic (5e-09) sample times are allowed in the subsystem.

I've attached the Simulink model too. Thanks!

Answer 1

[Kiran Kintali]

Some init scripts might be missing when I ctrl-d the model. For example I get the error.

 Variable 'activeLines' does not exist

There may be other missing variables. Can you share a compilable model?

It looks like you are also manually modeling AXIMasterRead and AXIMaterWrite. You can use additional automation

https://www.mathworks.com/help/hdlcoder/hardware-software-codesign-1.html?s_tid=CRUX_lftnav

https://www.mathworks.com/help/hdlcoder/ug/hardware-software-codesign-workflow-for-soc-platforms.html