Dave Gutierrez

Last seen: 10 mesi fa | Attivo dal 2012

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How do I add FPGA data capture IP core in existing Vivado project?
Hi Adriaan, If you are targeting a large board it might take a while to generate the bitstream. If you are not getting any erro...

oltre 4 anni fa | 0

Risposto
How do I add FPGA data capture IP core in existing Vivado project?
Adriaan, You need to add the generated HDL files to your project. It is not a Vivado IP. Thanks, David G

oltre 4 anni fa | 0

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dpigen: support for converting matlab fi data-type to systemverilog bit-vectors instead of shortint/int
Hi Krishnan, If you use the flag "-FixedPointDataType BitVector" or "-FixedPointDataType LogicVector" you can get the desired i...

quasi 5 anni fa | 0

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Communication Speed of "FPGA in the loop" in different communication ways?
-should I buy a new board with eth support or pcie support? yes. FIL supports PCIe and Ethernet. The supported hardware for X...

circa 5 anni fa | 0

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How can I get correct simulation result from generated SystemVerilog model in which DPI-C setparam function has vector parameter
1. The DPI-C component uses unpacked arrays so I will try removing the " ' " infront of " '{den3,den2,den1,den0} ". 2.Where a...

quasi 7 anni fa | 0

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