Adriaan Sadie

Last seen: oltre 4 anni fa | Attivo dal 2018

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Domanda

How do I add FPGA data capture IP core in existing Vivado project?
I am using the FPGA data capture component from Matlab (generateFPGADataCaptureIP) to generate a logic analyzer IP core which I ...

circa 5 anni fa | 2 risposte | 0

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Domanda

How can I access future samples of a discrete time signal in Simulink?
Hi I am busy with a project that implements model predictive control and it uses a reference signal's future sample values, i...

oltre 6 anni fa | 0 risposte | 0

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