Elaborate the Design Using Vivado | Getting Started with the Avnet ZUBoard, Part 3
From the series: Getting Started with the Avnet ZUBoard
Import a FIR filter IP block into AMD-Xilinx® Vivado® Design Suite and perform design validation. Then create a standalone design by adding inputs and outputs. Finally, validate the design and run behavioral simulation to make sure performance matches the previous step.
Published: 26 Aug 2022
Hello there. How would you like to validate and simulate an IP block with an AMD-Xilinx Vivavdo that you created from Vitis Model Composer? I'm John Pitrus with MathWorks. This is a four-part video series that covers getting started with the Avnet ZUBoard development kit.
In the first video, I showed you how to set up a project. In the second one, I showed you how to design an algorithm, a FIR filter, and then simulate it on your PC. In this video, we'll talk about how to elaborate the design for eventual FPGA implementation. And in the last video, I'll show you how to create the final bitstream file for programming your FPGA.
The main package we'll use today is Vivavdo from AMD-Xilinx. This is the back-end design platform that performs synthesis and place and route. The quality of the results are very good, and the compile time is very fast. If you want to learn more about Vivavdo, you can go to this link and you can download a trial copy, read about features and capabilities, and try some of the examples on your own. So with that, let's go ahead and start Vivavdo.
This is what the Home window looks like. We will create a new project. We'll go under Boards you look for our Avnet ZUBoard example, and there it is. We'll open that, and it will create the project for us.
Now that our project is initialized, we'll have to go into IP Repository and find the IP block that we created from Vitis Model Composer. So it found one project file. So I'll save that, and now it's a block within our library. And you can see when I go to the IP Catalog screen, our filter is right there. I can pull that up and tell Vivavdo to generate the block.
Next, I'll create the block, and we'll attach some I/Os and run validation. And lastly, we'll create this top-level player.
Now we're set to run a behavioral simulation, so we'll go ahead and do that. And it looks like that came back OK.
Let's review what we covered. In today's video, I showed you how to import an IP block into Vivavdo, create the interfaces in the hierarchy, and run a behavioral simulation. Now, since everything has passed, in the final video, I'll show you how to create a final bitstream and program the ZUBoard hardware. Thank you for watching.