HDL Coder™ generates portable, synthesizable VHDL® and Verilog® code from MATLAB® functions, Simulink® models, and Stateflow® charts. The generated HDL code can be used for FPGA programming or ASIC prototyping and design.
HDL Coder provides a workflow advisor that automates the programming of Xilinx®, Microsemi®, and Intel® FPGAs. You can control HDL architecture and implementation, highlight critical paths, and generate hardware resource utilization estimates. HDL Coder provides traceability between your Simulink model and the generated Verilog and VHDL code, enabling code verification for high-integrity applications adhering to DO-254 and other standards.
Support for industry standards is available through IEC Certification Kit (for ISO 26262 and IEC 61508).
Create a model and check compatibility for HDL code generation.
Generate VHDL and Verilog code from Simulink models.
Generate an HDL test bench to verify the VHDL or Verilog Code.
Generate code and synthesize your Simulink design on the target FPGA.
Workflow for HDL code generation and FPGA synthesis from MATLAB and Simulink algorithms.
How HDL Coder generates clock, reset, and clock enable signals in the HDL code.
HDL Coder Overview
Generate VHDL and Verilog code for FPGA and ASIC designs using HDL Coder
Using Simulink to Deploy a MATLAB Algorithm on an FPGA or ASIC
Learn how to take a MATLAB DSP algorithm through Simulink, Fixed-Point Designer™, and HDL Coder, and target an FPGA or ASIC