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Simulation and verification of generated HDL code using HDL test bench, cosimulation, or FPGA-in-the-loop

You can verify the generated code by using HDL test bench, cosimulation (requires HDL Verifier™), or FPGA-in-the-loop (requires HDL Verifier).

FPGA-in-the-loop (FIL) simulation allows you to run a Simulink® or MATLAB® simulation with an FPGA board strictly synchronized with this software. When you use FIL in the Workflow Advisor, HDL Coder™ uses the loaded design to create the HDL code. See FPGA-in-the-Loop (HDL Verifier).


HDL Test Bench



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