UVM Generation
Generate Universal Verification Methodology (UVM) test components and a behavioral design under test (DUT) from a Simulink model. You can use the generated components in two ways.
Generate a UVM top model with a test bench and a behavioral (DUT). Use the generated UVM top module as a test environment, and replace the generated behavioral DUT with your own simulation model.
Generate UVM test components, and integrate them into your existing UVM environment.
This feature requires Simulink Coder™.
Functions
uvmbuild | Generate UVM test bench from Simulink model |
Blocks
Sequence Feedback | Connect between scoreboard and sequence in UVM test bench model |
Objects
uvmcodegen.uvmconfig | UVM configuration object |
svdpiConfiguration | Configure workflows for UVM and SystemVerilog component generation from MATLAB |
Topics
- UVM Component Generation Overview
Generate a Universal Verification Methodology (UVM) environment from a Simulink model.
- Customize Generated UVM Code
Customize file banners and HDL simulation timescale when generating a UVM test bench.
- Generate SystemVerilog Assertions and Functional Coverage
Generate SystemVerilog immediate assertions from
verify
statements and model verification blocks, and collect functional coverage information (requires Simulink Test™ license). - Use Tunable Parameters to Generalize UVM Simulation
Generate UVM parameters from Simulink tunable parameters.
- Tunable Parameters in Sequence Subsystem
Generate random constraint parameters in UVM sequence from Simulink tunable parameters.
- Tunable Parameters in Scoreboard Subsystem
Generate random constraint parameters in UVM scoreboard from Simulink tunable parameters.
- SystemVerilog and UVM Template Engine
Generate customizable SystemVerilog modules and UVM components from MATLAB using templates.
- Template Engine Language Syntax
Template variable definition and usage.
- Generate Cross-Platform UVM Components
Generate the UVM components for a Linux® operating system from your Windows® host machine.