Demux
Extract and output elements of virtual vector signal
- Library:
Simulink / Commonly Used Blocks
Simulink / Signal Routing
HDL Coder / Commonly Used Blocks
HDL Coder / Signal Routing
Description
The Demux block extracts the components of an input vector signal and outputs separate signals. The output signal ports are ordered from top to bottom.
Ports
Input
Port_1
— Accept nonbus vector signal to extract and output signals
from
real or complex values of any nonbus data type supported by
Simulink®
Vector input signal from which the Demux block selects scalar signals or smaller vectors.
Data Types: single
| double
| half
| int8
| int16
| int32
| int64
| uint8
| uint16
| uint32
| uint64
| Boolean
| fixed point
| enumerated
| image
Output
Port_1
— Output signals extracted from input vector signal
nonbus signal with real or complex values of any data type supported
by Simulink
Output signals extracted from the input vector. The output signal ports are ordered from top to bottom. See Port Location After Rotating or Flipping for a description of the port order for various block orientations.
Data Types: single
| double
| half
| int8
| int16
| int32
| int64
| uint8
| uint16
| uint32
| uint64
| Boolean
| fixed point
| enumerated
| image
Parameters
Number of outputs
— Number of outputs
2 (default) | scalar | vector
Specify the number of outputs and, optionally, the dimensionality of each output port.
The value can be a scalar specifying the number of outputs or a vector whose elements specify the widths of the block output ports. The block determines the size of its outputs from the size of the input signal and the value of the Number of outputs parameter.
If you specify a scalar for the Number of outputs parameter, and all of the output ports are connected, as you draw a new signal line close to the output side of a Demux block, Simulink adds a port and updates the Number of outputs parameter.
For an input vector of width n
, this table describes what the
block outputs.
Parameter Value | Block outputs... | Examples and Comments |
---|---|---|
|
| If the input is a three-element vector and you specify three outputs, the block outputs three scalar signals. |
| Error | This value is not supported. |
|
| If the input is a six-element vector and you specify three outputs, the block outputs three two-element vectors. |
|
| If the input is a five-element vector and you specify three outputs, the block outputs two two-element vector signals and one scalar signal. |
|
| If the input is a five-element vector and you specify |
An array that has one or more of For example,
suppose that you have a four-element array with a total width of 14 and you
specify the parameter to be
The
value for the third element (the |
| If |
| Error | This value is not supported |
If you specify a number of outputs that is smaller than the number of input elements, the block distributes the elements as evenly as possible over the outputs. For examples, see Extract Vector Elements and Distribute Evenly Across Outputs and Extract Vector Elements Using the Demux Block.
Programmatic Use
Block Parameter:
Outputs |
Type: scalar or vector |
Values: character vector |
Default:
{'2'} or vector |
Display option
— Displayed block icon
bar
(default) | none
By default, the block icon is a solid bar of the block foreground color.
To display the icon as a box containing the block type name, select
none
.
Programmatic Use
Block Parameter:
Display option |
Type: character vector |
Values:
'bar' | 'none' |
Default:
'bar' |
Model Examples
Block Characteristics
Data Types |
|
Direct Feedthrough |
|
Multidimensional Signals |
|
Variable-Size Signals |
|
Zero-Crossing Detection |
|
Extended Capabilities
C/C++ Code Generation
Generate C and C++ code using Simulink® Coder™.
Actual data type or capability support depends on block implementation.
HDL Code Generation
Generate Verilog and VHDL code for FPGA and ASIC designs using HDL Coder™.
HDL Coder™ provides additional configuration options that affect HDL implementation and synthesized logic.
This block has one default HDL architecture.
ConstrainedOutputPipeline | Number of registers to place at
the outputs by moving existing delays within your design. Distributed
pipelining does not redistribute these registers. The default is
|
InputPipeline | Number of input pipeline stages
to insert in the generated code. Distributed pipelining and constrained
output pipelining can move these registers. The default is
|
OutputPipeline | Number of output pipeline stages
to insert in the generated code. Distributed pipelining and constrained
output pipelining can move these registers. The default is
|
This block supports code generation for complex signals.
PLC Code Generation
Generate Structured Text code using Simulink® PLC Coder™.
Fixed-Point Conversion
Design and simulate fixed-point systems using Fixed-Point Designer™.
Actual data type or capability support depends on block implementation.
Version History
Introduced before R2006a
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