Implement zero-order hold sample period
Simulink / Discrete
HDL Coder / Discrete
The Zero-Order Hold block holds its input for the sample period you specify. If the input is a vector, the block holds all elements of the vector for the same sample period.
You specify the time between samples with the Sample time parameter. A setting of
the block inherits the Sample time.
Do not use the Zero-Order Hold block to create a fast-to-slow transition between blocks operating at different sample rates. Instead, use the Rate Transition block.
The Zero-Order Hold block is a bus-capable block. The input can be a virtual or nonvirtual bus signal. No block-specific restrictions exist. All signals in a nonvirtual bus input to a Zero-Order Hold block must have the same sample time, even if the elements of the associated bus object specify inherited sample times. You can use a Rate Transition block to change the sample time of an individual signal, or of all signals in a bus. See Specify Bus Signal Sample Times and Bus-Capable Blocks for more information.
You can use an array of buses as an input signal to a Zero-Order Hold block. For details about defining and using an array of buses, see Combine Buses into an Array of Buses.
The Memory, Unit Delay, and Zero-Order Hold blocks provide similar functionality but have different capabilities. Also, the purpose of each block is different.
This table shows recommended usage for each block.
|Block||Purpose of the Block||Reference Examples|
|Unit Delay||Implement a delay using a discrete sample time that you specify. The block accepts and outputs signals with a discrete sample time.||
|Memory||Implement a delay by one major integration time step. Ideally, the block accepts continuous (or fixed in minor time step) signals and outputs a signal that is fixed in minor time step.|
|Zero-Order Hold||Convert an input signal with a continuous sample time to an output signal with a discrete sample time.|
Each block has the following capabilities.
|Capability||Memory||Unit Delay||Zero-Order Hold|
|Specification of initial condition||Yes||Yes||No, because the block output at time t = 0 must match the input value.|
|Specification of sample time||No, because the block can only inherit sample time from the driving block or the solver used for the entire model.||Yes||Yes|
|Support for frame-based signals||No||Yes||Yes|
|Support for state logging||No||Yes||No|
Port_1— Input signal
Input signal that the block holds by one sample period.
fixed point |
Port_1— Output signal
Output signal that is the input held by one sample period.
fixed point |
Sample time (-1 for inherited)— Discrete interval between sample time hits
Specify the time interval between samples. To inherit the sample time, set
this parameter to
-1. See Specify Sample Time in the
online documentation for more information.
Do not specify a continuous sample time, either
[0,0]. This block supports only discrete sample
times. When this parameter is
-1, the inherited sample
time must be discrete and not continuous.
Generated code relies on
strong.h) under certain conditions.
For information about HDL code generation, see Zero-Order Hold.