Detect Common Design Errors

Open Live Script

Before you perform design error detection analysis, check the model for defects using Defect checker. Defect checker reports the number of defects in your model throughout the development phase for common and critical design errors such as division by zero, integer overflow, dead logic, and array out of bounds.

Use Defect Checker

Open the model sldvexDetectDesignErrorsExample. On the Design Verifier tab, verify that Defect Checker is selected.

Alternatively, in the Configuration Parameters dialog box, on the Design Verifier > Design Error Detection pane, verify that Defect Checker is selected.

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Perform Analysis

To detect common design errors by using Defect Checker, on the Design Verifier tab, click Detect Design Errors.

Simulink Design Verifier analyzes sldvexDetectDesignErrorsExample model for the defects and displays the number of defects found during the analysis in the Results Summary window.

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The analysis results indicate that there are three defects in the model. You can view the detailed analysis report by clicking HTML or PDF in the Results Summary window. The report shows run-time error objectives with the counterexamples for Sum, Divide, and Abs blocks. For more information on the objective status, see Review Results.

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The Analysis Information chapter in the report indicates that the defect checker analysis performed a simplified checking of common defects.