Zynq and FMCOMMS2/3/4 Transmitter Configuration
Connect hardware logic to FMCOMMS Zynq radio transmitter hardware
Use of this block is not recommended. Use AD936x Data Write instead. For more information, see Version History.
Add-On Required: This feature requires the SoC Blockset Support Package for AMD FPGA and SoC Devices add-on.
Libraries:
SoC Blockset Support Package for Xilinx Devices /
MPSoC /
ZCU102
SoC Blockset Support Package for Xilinx Devices /
Zynq-7000 /
ZC706
SoC Blockset Support Package for Xilinx Devices /
Zynq-7000 /
ZedBoard
Description
The Zynq and FMCOMMS2/3/4 Transmitter Configuration block connects your hardware logic to the FMCOMMS2/3/4 radio transmitter hardware. In simulation, this block provides optional ports for center frequency and gain, which the SoC Builder tool maps to hardware pins. The block does not connect to the radio hardware from simulation.
Examples
Packet-Based ADS-B Transceiver
Packet-based systems are common in wireless communications. Data is received over the air and is decoded as discrete packet data on a compute device. For given system requirements, it is difficult to design a system and implement directly on SoC as it often involves long iterations of debugging and integration on hardware since hardware effects are difficult to account for at design time. In this example, you will design packet-based airplane tracking application based on Automatic Dependent Surveillance Broadcast (ADS-B) standard, partitioned between FPGA and embedded processor. Unlike traditional methods, you will simulate the application design with memory interface before implementation on hardware using SoC Blockset™ to shorten development time. You will then validate the design on hardware by automatically generated code from the model.
Transmit and Receive Tones Using AD9361 Dual-Channels
Design, simulate, and deploy dual-channel application system with AD9361 RF card using SoC Blockset™ on Xilinx® Zynq® UltraScale+™ MPSoC ZCU102 Evaluation Kit.
Limitations
In the hardware setup, select one of the supported Xilinx boards. You can find the supported boards in the Libraries list at the top of this page. Set Add-on Card to
None.This block supports SoC generation using the SoC Builder tool. This block does not support the IP core generation workflow. For more information on workflows, see SoC Generation Workflows.
