HDL IP Core generation for Xilinx Vivado fails since the year turned from 2021 to 2022

Question

5 voti

Since returning to the office in 2022, I have been unable to use HDL Workflow Advisor with Xilinx Vivado. I see the following error message in HDL Workflow Advisor in Task 3.2:

Failed Task "Vivado IP Packager" unsuccessful. See log for details. Generated logfile: hdl_prj\hdlsrc\modelname\workflow_task_VivadoIPPackager.log
Error using hdlturnkey.ip.IPEmitterVivado/packageVivadoIP
Task "Vivado IP Packager" unsuccessful. See log for details.
Generated logfile: hdl_prj\hdlsrc\modelname\workflow_task_VivadoIPPackager.log
Error in hdlturnkey.ip.IPEmitterVivado/generateIPCore
Error in hdlturnkey.ip.IPDriver/generateIPCore
Error in hdlturnkey.TurnkeyDriver/makehdlturnkeycore
Error in hdlturnkey.TurnkeyDriver/makehdlturnkey
Error in slhdlcoder.HDLCoder/makehdlturnkey
Error in downstream.DownstreamIntegrationDriver/runIPCoreCodeGen
Error in generateIPCore
Error in Simulink.ModelAdvisor/executeCheckCallbackFct
Error in Simulink.ModelAdvisor/run
Error in Simulink.ModelAdvisor/runCheck
Error in ModelAdvisor.Node/runTaskAdvisor
Error in ModelAdvisor.Node.run

If I check the log at \hdl_prj\hdlsrc\modelname\workflow_task_VivadoIPPackager.log, I see the following error message:

"bad lexical cast: source type value could not be interpreted as target while executing"

Task "Vivado IP Packager" unsuccessful. See log for details.
Generated logfile: 
****** Vivado v2018.3 (64-bit)
  **** SW Build 2405991 on Thu Dec  6 23:38:27 MST 2018
  **** IP Build 2404404 on Fri Dec  7 01:43:56 MST 2018
    ** Copyright 1986-2018 Xilinx, Inc. All Rights Reserved.
source vivado_ip_package.tcl -notrace
INFO: [IP_Flow 19-234] Refreshing IP repositories
INFO: [IP_Flow 19-1700] Loaded user IP repository 'c:/Users/Li/Desktop/Mankov/hdl_prj/ipcore'.
WARNING: [IP_Flow 19-3656] If you move the project, the path for repository 'c:/Users/Li/Desktop/Mankov/hdl_prj/ipcore' may become invalid. A better location for the repository would be in a path adjacent to the project. (Current project location is 'c:/Users/Li/Desktop/Mankov/hdl_prj/ipcore/DUT_IO33x_IP_v1_0/prj_ip'.)
INFO: [IP_Flow 19-2313] Loaded Vivado IP repository 'C:/Xilinx/Vivado/2018.3/data/ip'.
INFO: [IP_Flow 19-5107] Inferred bus interface 'DMA_Stream_FPGA_to_CPU_Master' of definition 'xilinx.com:interface:axis:1.0' (from Xilinx Repository).
INFO: [IP_Flow 19-5107] Inferred bus interface 'AXI4_Lite' of definition 'xilinx.com:interface:aximm:1.0' (from Xilinx Repository).
INFO: [IP_Flow 19-5107] Inferred bus interface 'AXI4_Lite_ARESETN' of definition 'xilinx.com:signal:reset:1.0' (from Xilinx Repository).
INFO: [IP_Flow 19-5107] Inferred bus interface 'IPCORE_RESETN' of definition 'xilinx.com:signal:reset:1.0' (from Xilinx Repository).
INFO: [IP_Flow 19-5107] Inferred bus interface 'AXI4_Lite_ACLK' of definition 'xilinx.com:signal:clock:1.0' (from Xilinx Repository).
INFO: [IP_Flow 19-5107] Inferred bus interface 'IPCORE_CLK' of definition 'xilinx.com:signal:clock:1.0' (from Xilinx Repository).
INFO: [IP_Flow 19-4728] Bus Interface 'AXI4_Lite_ARESETN': Added interface parameter 'POLARITY' with value 'ACTIVE_LOW'.
INFO: [IP_Flow 19-4728] Bus Interface 'IPCORE_RESETN': Added interface parameter 'POLARITY' with value 'ACTIVE_LOW'.
INFO: [IP_Flow 19-4728] Bus Interface 'AXI4_Lite_ACLK': Added interface parameter 'ASSOCIATED_BUSIF' with value 'AXI4_Lite'.
INFO: [IP_Flow 19-4728] Bus Interface 'AXI4_Lite_ACLK': Added interface parameter 'ASSOCIATED_RESET' with value 'AXI4_Lite_ARESETN'.
INFO: [IP_Flow 19-4728] Bus Interface 'IPCORE_CLK': Added interface parameter 'ASSOCIATED_RESET' with value 'IPCORE_RESETN'.
WARNING: [IP_Flow 19-3158] Bus Interface 'DMA_Stream_FPGA_to_CPU_Master': FREQ_HZ bus parameter missing from AXI interface when interface is not associated to a clock.
WARNING: [IP_Flow 19-3153] Bus Interface 'IPCORE_CLK': ASSOCIATED_BUSIF bus parameter is missing.
INFO: [IP_Flow 19-2181] Payment Required is not set for this core.
INFO: [IP_Flow 19-2187] The Product Guide file is missing.
bad lexical cast: source type value could not be interpreted as target
    while executing"rdi::set_property core_revision 2201031458 {component component_1}"
    invoked from within
"set_property core_revision 2201031458 [ipx::current_core]"
    (file "vivado_ip_package.tcl" line 57)
INFO: [Common 17-206] Exiting Vivado at Mon Jan  3 14:58:23 2022...
Elapsed time is 12.568 seconds.