How to use AXI stream interfaces in xilinx system generator?

HI there, I want know if AXI stream interfaces can be used in xilinx system generator model for a single input port? If yes, then how can we go about doing that? Thanks in advance..

Answer 1

[Graham Naylor]

Yes. While the gateway blocks can be configured to be axi-lite registers, it is not clear how to use AXI-stream. It can however be done and is relatively simple. You do have to provide the handshaking signals tvalid and tready - ie you need to use 3 gateways (perhaps 4 - see below) per port. For a streaming input you need then a data input gateway and give it a name something like myvalues_in_tdata a strobe input called myvalues_in_tvalid which can be used to latch the data in the System generator model (eg in a FIFO) and you need to provide a gateway out called myvalues_in_ready that you set boolean true when you are ready to receive (eg from FIFO not full, or less than 75% full or whatever). To stream out you check that a gateway in, that you call myvalues_out_tready, is high and put data on a gateway out called something like myvalues_out_tdata and provide a gateway out called myvalues_out_tvalid that is asserted for one clock cycle of your axi bus. Now just to add one more complexity, there is a gateway *_tlast that you should probably also use - certainly when streaming out. This gateway out ( would be asserted simultaneously with the last tvalid of the bunch of data you want to stream. You may or may not want to look at tlast on data streaming in as you may or may not be interested in packets. You are however likely to need to provide tlast on data streamed out if the data is to be read by a processor that likes to receive data in chunks (packets). Using the naming style above (with _tvalid etc), if you package the System Generator model in to an IP you will see the AXI streaming ports grouped together as an AXI bus in IP Integrator of Vivado.

[Shashi TG]

Thank you , that was very helpful to me. Can _tvalid , _tready and _tlast to the gateway_out ports can be given from the Output of the AXI fifo placed at the input of the design? I am i right?

[Graham Naylor]

Yes, you can either connect them individually, or if the SysGen design is packaged for IP integrator it should be possible to see the 4 gateways presented as a single bus by the IP packager.