Getting timing closure for HDL Coder IP with multicycle paths

3 visualizzazioni (ultimi 30 giorni)
I have created an IP component with HDL Coder and I have integrated this into a Vivado project but I am struggling to get timing closure using multicycle paths.
The FPGA clock rate is set at 50MHz. The IP block carries out some reasonably complex fixed point computations at a slower rate of 250KHz. There are 200 clock cycles to complete these computations. Within the computations there are some 1/Z feedback loops as the calculations for the current cycle depend on the results from the previous cycle. There is also some trivial logic that runs in a single cycle at the 50MHz rate. So, the IP model block has 2 rates; 50MHz and 250KHz. Also, some of the slower rate computations are pipelined on 4 paths so in the HDL Coder generated model there are rates of 50MHz, 250KHz and 1MHz as a result of the pipelining. I have surrounded the slower functionality with 1/Z delays as suggested in the help for multicycle paths.
When I generate the IP block I get a timing controller file _tc.vhd with clock enables at 50 and 200 times slower than the base FPGA clock rate.
model.jpg
-- enb_1_1_1 : identical to clk_enable
-- enb_1_50_0 : 50x slower than clk with last phase
-- enb_1_200_0 : 200x slower than clk with last phase
-- enb_1_200_1 : 200x slower than clk with phase 1
--
ATTRIBUTE keep OF phase_0 : SIGNAL IS "true";
ATTRIBUTE mcp_info OF phase_0 : SIGNAL IS "SpeedsVibsProc_tc.u1_d50_o0";
ATTRIBUTE keep OF phase_0_1 : SIGNAL IS "true";
ATTRIBUTE mcp_info OF phase_0_1 : SIGNAL IS "SpeedsVibsProc_tc.u1_d200_o0";
I also generate a multicycle constraints file as follows:
# Multicycle constraints for clock enable: SpeedsVibsProc_tc.u1_d50_o0
set enbregcell [get_cells -hier -filter {mcp_info=="SpeedsVibsProc_tc.u1_d50_o0"}]
set enbregnet [get_nets -of_objects [get_pins -of_objects $enbregcell -filter {DIRECTION == OUT}]]
set reglist [get_cells -of [filter [all_fanout -flat -endpoints_only $enbregnet] IS_ENABLE]]
set_multicycle_path 50 -setup -from $reglist -to $reglist -quiet
set_multicycle_path 49 -hold -from $reglist -to $reglist -quiet
# Multicycle constraints for clock enable: SpeedsVibsProc_tc.u1_d200_o0
set enbregcell [get_cells -hier -filter {mcp_info=="SpeedsVibsProc_tc.u1_d200_o0"}]
set enbregnet [get_nets -of_objects [get_pins -of_objects $enbregcell -filter {DIRECTION == OUT}]]
set reglist [get_cells -of [filter [all_fanout -flat -endpoints_only $enbregnet] IS_ENABLE]]
set_multicycle_path 200 -setup -from $reglist -to $reglist -quiet
set_multicycle_path 199 -hold -from $reglist -to $reglist -quiet
I then build the IP block into a Vivado project and build the design; also adding the muticycle constraints file to the project. However, the design fails to meet the timing constraints with some paths with a WNS of around -66ns.
I have manually entered the commands from the constraints file in the TCL command window and all seems fine; no errors or warnings.
If I open up one of the failing paths and look at the schematic I see a very long set of linked blocks and it seems that these are somehow related to the 1/Z feedbacks within the calculations.
Is there anything I can do the model design to make the timing closure easier? Do I need to manually create a different multicycle paths constraints file for example?

Risposta accettata

Kiran Kintali
Kiran Kintali il 21 Set 2019
Please contact support@mathworks.com for help on this topic. Can you share the Simulink model with us to better answer the question?

Più risposte (0)

Prodotti


Release

R2019a

Community Treasure Hunt

Find the treasures in MATLAB Central and discover how the community can help you!

Start Hunting!

Translated by