How to have multiple clock inputs on IP Core generated by HDL Coder?
3 visualizzazioni (ultimi 30 giorni)
Mostra commenti meno recenti
I need to have 2 clock inputs on IP Core generated by HDL Coder.
Vivado allows it, but HDL Coder flags an error and demands to change settings to a single clock input.
Why would HDL Coder do that while Xilinx allows IP Core with multiple clock inputs?
Any adwise?
0 Commenti
Risposte (0)
Vedere anche
Community Treasure Hunt
Find the treasures in MATLAB Central and discover how the community can help you!
Start Hunting!