hdl coder model checker output latetency and ulp error warning
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Fahri Gürbüz
il 29 Giu 2020
Risposto: Kiran Kintali
il 19 Ott 2020
Hi,
I am trying to generate motor speed controller in FPGA. I have completed my model and now I am in code generation phase. It is the first time I am using hld coder. Thus, some warnings are still question mark for me. While I have run model checker, following warning are appeared
Warn : Check for blocks with nonzero output latency
Message : Following Blocks have non-zero output latency
Minimum latency is 6, and maximum latency is 11 for : sim2fpga_2/subsystem/abc2qd/Add2
Minimum latency is 6, and maximum latency is 11 for : sim2fpga_2/subsystem/abc2qd/Add3
Minimum latency is 6, and maximum latency is 11 for : sim2fpga_2/subsystem/abc2qd/Add4
Minimum latency is 6, and maximum latency is 11 for : sim2fpga_2/subsystem/abc2qd/Add5
Minimum latency is 6, and maximum latency is 11 for : sim2fpga_2/subsystem/abc2qd/Add6
Minimum latency is 6, and maximum latency is 11 for : sim2fpga_2/subsystem/abc2qd/Add7
Minimum latency is 6, and maximum latency is 6 for : sim2fpga_2/subsystem/abc2qd/Data Type Conversion
Minimum latency is 6, and maximum latency is 6 for : sim2fpga_2/subsystem/abc2qd/Data Type Conversion1
Minimum latency is 6, and maximum latency is 8 for : sim2fpga_2/subsystem/abc2qd/Divide1
Minimum latency is 6, and maximum latency is 8 for : sim2fpga_2/subsystem/abc2qd/Divide2
Minimum latency is 6, and maximum latency is 8 for : sim2fpga_2/subsystem/abc2qd/Divide3
Minimum latency is 6, and maximum latency is 8 for : sim2fpga_2/subsystem/abc2qd/Divide4
Minimum latency is 6, and maximum latency is 8 for : sim2fpga_2/subsystem/abc2qd/Divide5
Minimum latency is 6, and maximum latency is 8 for : sim2fpga_2/subsystem/abc2qd/Divide6
Minimum latency is 27, and maximum latency is 27 for : sim2fpga_2/subsystem/abc2qd/cos(theta+120)
Minimum latency is 27, and maximum latency is 27 for : sim2fpga_2/subsystem/abc2qd/cos(theta-120)
Minimum latency is 27, and maximum latency is 27 for : sim2fpga_2/subsystem/abc2qd/costheta
Minimum latency is 27, and maximum latency is 27 for : sim2fpga_2/subsystem/abc2qd/sin(theta+120)1
Minimum latency is 27, and maximum latency is 27 for : sim2fpga_2/subsystem/abc2qd/sin(theta-120)1
Minimum latency is 27, and maximum latency is 27 for : sim2fpga_2/subsystem/abc2qd/sintheta1
and
Warn : Check blocks with nonzero ulp error
Warning : Following Blocks have non-zero ULP Error
Error is 2 in sim2fpga_2/subsystem/abc2qd/cos(theta+120)
Error is 2 in sim2fpga_2/subsystem/abc2qd/cos(theta-120)
Error is 2 in sim2fpga_2/subsystem/abc2qd/costheta
Error is 2 in sim2fpga_2/subsystem/abc2qd/sin(theta+120)1
Error is 2 in sim2fpga_2/subsystem/abc2qd/sin(theta-120)1
Error is 2 in sim2fpga_2/subsystem/abc2qd/sintheta1
Could you help me about How I can get rid of these warnings?
Thanks in advance,
Regards,
Fahri
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Risposta accettata
Kiran Kintali
il 19 Ott 2020
These are messages informing about blocks that introduce latency. In case you have such blocks in feedback loops you need to take necessary actions such as using oversamping factor or handle latency matching process. No action necessary if you do not have any code generation errors.
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