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Andrew
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HDL Coder reset control

Asked by Andrew
on 8 Feb 2013
Latest activity Commented on by luckfy zhang on 21 Apr 2018
Hi, Simulink HDL Coder: is it possible to control the generation of the vhdl reset clause on a block by block basis?
In general, most flops in a datapath design dont require reset. we just reset the input of datapath, and wait long enough for the known input to propagate through the datapath and put the design in a well defined state. Anything with feedback requires a reset. By using reset only when required like this, we save fpga routing resource, and produce more efficient, higher performance designs.
However,HDL coder produces vhdl with a reset on every flop. (we use sychronous reset). Is there a way for us to prevent hdl coder adding resets on all flops? can we control it?
cheers andrew

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1 Answer

Answer by Tim McBrayer on 11 Feb 2013
Edited by Tim McBrayer on 28 Feb 2017
 Accepted Answer

Andrew,
There is a block-level parameter that allows the reset to be disabled on a block by block basis. You can access this parameter by right-clicking on a Delay block and choosing HDL Code -> HDL Block Properties. On this dialog, change ResetType from 'default' to 'none'. This sets the register generated from that Delay block to be generated with no reset.
The ResetType block parameter chooses whether a block will generate a reset or not. 'None' will not generate a reset; 'default' will generate whatever sort of reset is configured for HDL Coder in its Global Settings Configuration Parameters pane.
Since you have stated that you want the default to be no reset, the GUI-based interactive approach will be tedious. To script this, you can use the hdlset_param command, which has the syntax:
hdlset_param(block, parameter, value)
You can combine this with find_system to set all the Delay blocks in your model to have no reset:
hdlset_param(find_system('modelname', 'BlockType', 'Delay'), 'ResetType', 'none')
This will change the value of the HDL block parameter on all Delay blocks in your model to 'none'. Block parameters are persistent and are saved in the model, so this should be a one-time configuration. You can then go back and re-add a reset to those Delay blocks that require it.

  3 Comments

I was thinking the same thing about the default reset signal and FPGA efficiency (I only want to reset the registers I deem necessary). I needed to modify Tim's line of code to do what I wanted though:
hdlset_param(find_system('modelname', 'LookUnderMasks', 'all', 'BlockType', 'Delay'), 'ResetType', 'none')
% (fixes missing ' and goes inside all masks)
Also, I needed to run this for the model and the library (I tried using 'FollowLinks', 'on', but that gave me a lot of warnings saying I had to push the change into the library anyway, so it was easier to do it just to the library in the first place).
I recommend checking the HDL code for a reset signal you didn't delete with the operation above. In my case, I'm still using 'simulink/Additional Math & Discrete/Additional Discrete/Unit Delay Enabled' (obsolete but functioning in 2016b) instead of a delay block with show enable port option (I'll post separately on my confusion on this topic - "Delay with Show Enable Port not working as expected").
Tim McBrayer on 28 Feb 2017
Good catch; I fixed my statement to match yours.
luckfy zhang on 21 Apr 2018
Hello, you answer seems do not applicable for me since there are only asynchronous and synchronous choice for ResetType. And I cannot set this parameter to none. My Matlab version is R2015b. Could you provide me for some help?

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