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Propagation of signals in RF Data Converter block in simulation and on hardware
Hi @Sergei, In the attached model, the RFDC simulation is set to "Pass-through", in this mode the ADC output is same as the D...
Propagation of signals in RF Data Converter block in simulation and on hardware
Hi @Sergei, In the attached model, the RFDC simulation is set to "Pass-through", in this mode the ADC output is same as the D...
5 mesi fa | 2
| accettato
Risposto
RF Data Converter: input/output data types
Hi @Sergei, Here are my repsonses to your questions. #1) On hardware, the output level of ADC depends on the input analog ...
RF Data Converter: input/output data types
Hi @Sergei, Here are my repsonses to your questions. #1) On hardware, the output level of ADC depends on the input analog ...
5 mesi fa | 1
| accettato
Risposto
Help to understand RF Data Converter clocking
Hi @Sergei, The FPGA sample time must always match the stream clock frequency shown on RF Data Converter block mask. From...
Help to understand RF Data Converter clocking
Hi @Sergei, The FPGA sample time must always match the stream clock frequency shown on RF Data Converter block mask. From...
5 mesi fa | 2
| accettato
Risposto
Usage of SoC Blockset with custom Vivado Block Design
Hi Samuel, Yes, it is possible to create a custom board without processing system. You can refer the custom board example. You ...
Usage of SoC Blockset with custom Vivado Block Design
Hi Samuel, Yes, it is possible to create a custom board without processing system. You can refer the custom board example. You ...
circa 3 anni fa | 0
| accettato
Risposto
Custom board ZCU104 fails to load in external mode
To register sysroot, run the following command. Make sure you provide the board support name you used during ZCU104 board suppor...
Custom board ZCU104 fails to load in external mode
To register sysroot, run the following command. Make sure you provide the board support name you used during ZCU104 board suppor...
circa 3 anni fa | 0
Risposto
socModelCreator failed to generate design
Vivado has a bug that it will errors out to say an IP does not support Zynq RFSoC family even though the IP says it supports it....
socModelCreator failed to generate design
Vivado has a bug that it will errors out to say an IP does not support Zynq RFSoC family even though the IP says it supports it....
circa 3 anni fa | 0
