Video e Webinar

HDL Coder Clock Rate Pipelining, Part 1: Introduction

Jack Erickson, MathWorks

Part one of this two-part series on clock rate pipelining discusses:

Why clock rate pipelining is needed
Why pipeline stages need to be inserted into designs that target an FPGA
How sample rates in Simulink^® map to clock rates on an FPGA
How to use oversampling in HDL Coder™ to scale up Simulink data rates to faster FPGA clock rates
How clock rate pipelining works

Part two of this series demonstrates how to combine clock rate pipelining with other HDL Coder optimizations to trade off speed versus resource usage.

Product Focus

HDL Coder

Related Products

HDL Coder

Related Videos and Webinars

HDL Coder Clock Rate Pipelining, Part 2: Optimization

Using HDL Coder and HDL Verifier for FPGA and ASIC Designs

Programming Intel SoC FPGAs with Embedded Coder and HDL...

Rapid Prototyping Using HDL Coder

HDL Coder State Control Block

Rapid Prototyping Using HDL Coder (Highlights)

Map Tunable Parameters to AXI4 Interface with HDL Coder

What Is HDL Coder?

Using Xilinx System Generator for DSP with Simulink and HDL...

Accelerate Design Space Exploration Using HDL Coder...

FFT and IFFT HDL Optimized GSPS Signal Processing

HDL Implementation and Verification of a High-Performance...

Introduction to FPGA Design Using MATLAB and Simulink

Implementing a Wireless Receiver on an FPGA, Part 2:...

Implementing a Wireless Receiver on an FPGA, Part 3:...

Implementing a Wireless Receiver on an FPGA, Part 1:...

Introduction to Filter Design HDL Coder

Radio Testbed Design Using HDL Coder

Implementation of Algorithm for Extension of Unambiguous...

Introduction to Embedded Coder for BeagleBone Black