Design a Model for AXI4 Interfaces

Model your algorithm in Simulink^® by using a simplified protocol for mapping to AXI4-Stream, AXI4-Stream Video, or AXI4 Master interfaces

With the HDL Coder™ software, you can implement a simplified protocol in your model for AXI4-Stream, AXI4-Stream Video, or AXI4 Master mapping. The software generates an HDL IP core with the corresponding interfaces.

Topics

Model Design for AXI4 Slave Interface Generation
How to design your model for AXI4 or AXI4-Lite interfaces for scalar, vector ports, bus data types, and read back values.
Model Design for AXI4-Stream Interface Generation
How to design your model for AXI4-Stream vector or scalar interface generation.
Model Design for AXI4-Stream Video Interface Generation
How to design your model for IP core generation with AXI4-stream video interfaces.
Model Design for AXI4 Master Interface Generation
Description of AXI4 Master protocol, and how you can design your model for IP core generation with AXI4-Master interfaces.
Save Target Hardware Settings in Model
This example shows how to save your target hardware settings in a Simulink® model.

Featured Examples

Deploy Model with AXI-Stream Interface in Zynq Workflow

Use the AXI4-Stream interface to enable high speed data transfer between the processor and FPGA on Zynq^® hardware.

Open Script

Deploy Model with AXI4-Stream Video Interface on Zynq Hardware

Use the AXI4-Stream Video interface to enable high speed video streaming on the generated HDL IP core.

Open Live Script

Offload Large Delays from Frame-Based Models to External Memory

Map large delays to external memory when generating an IP core from a frame-based algorithm.

Open Live Script