HDL File Names and Locations

Setting the Location of Generated Files

By default, the coder places generated HDL files in the subfolder hdlsrc under your current working folder. To direct the coder output to a folder other than the default target folder, use either the Folder field or the Browse button in the Target pane of the Generate HDL tool.

Clicking the Browse button opens a browser window that lets you select (or create) the folder where the coder puts generated files. When the folder is selected, the full path and folder name are automatically entered into the Folder field.

Alternatively, you can enter the folder specification directly into the Folder field. If you specify a folder that does not exist, the coder creates the folder for you before writing the generated files. Your folder specification can be one of these formats.

Folder name. In this case, the coder looks for the subfolder under your current working folder. If it cannot find the specified folder, the coder creates it.
An absolute path to a folder under your current working folder. If the coder cannot find the specified folder, the coder creates it.
A relative path to a higher-level folder under your current working folder. For example, if you specify ../../../myfiltvhd, the coder checks whether a folder named myfiltvhd exists three levels up from your current working folder. The coder then creates the folder if it does not exist, and writes generated HDL files to that folder.

In this figure, the folder is set to MyFIRBetaVHDL.

Target section of Generate HDL tool

Given this setting, the coder creates the subfolder MyFIRBetaVHDL under the current working folder and writes generated HDL files to that folder.

Command-Line Alternative: Use the generatehdl function with the TargetDirectory property to redirect coder output.

Naming the Generated Files and Filter Entity

To set the character vector that the coder uses to name the filter entity or module and generated files, specify a new value in the Name field of the Filter settings pane of the Generate HDL tool. The coder uses Name to:

Label the VHDL^® entity or Verilog^® module for your filter.
Name the file containing the HDL code for your filter.
Derive names for the filter's test bench and package files.

Derivation of File Names

By default, the coder creates the HDL files listed in the table. File names in generated HDL code derive from the name of the filter for which the HDL code is being generated and the file type extension .vhd or .v for VHDL and Verilog, respectively. The table lists example file names based on filter name Hq.

Language	Generated File	File Name	Example
Verilog	Source file for the quantized filter	`filt_name.v`	`firfilt.v`
Verilog	Source file for the test bench	`filt_name_tb.v`	`firfilt_tb.v`
VHDL	Source file for the quantized filter	`filt_name.vhd`	`firfilt.vhd`
	Source file for the test bench	`filt_name_tb.vhd`	`firfilt_tb.vhd`
	Package file, if required by the filter design	`filt_name_pkg.vhd`	`firfilt_pkg.vhd`

By default, the coder generates a single test bench file, containing test bench helper functions, data, and test bench code. You can split these elements into separate files, as described in Splitting Test Bench Code and Data into Separate Files.

By default, the code for a VHDL entity and architecture is written to a single VHDL source file. Alternatively, you can specify that the coder write the generated code for the entity and architectures to separate files. For example, if the filter name is filt_name, the coder writes the VHDL code for the filter to files filt_name_entity.vhd and filt_name_arch.vhd (see Splitting Entity and Architecture Code Into Separate Files).

Derivation of Entity Names

The coder also uses the filter name to name the VHDL entity or Verilog module that represents the quantized filter in the HDL code. Assuming a filter name of filt, the name of the filter entity or module in the HDL code is filt.

Set HDL File Name Extensions

Set File Name Extension Via the Generate HDL Tool
Set HDL File Name Extensions Via the Command-Line

Set File Name Extension Via the Generate HDL Tool

When you select VHDL code generation, by default the filter HDL files are generated with a .vhd file extension. When you select Verilog, the default file extension is .v. To change the file extension,

Select the Global Settings tab on the Generate HDL tool.
Select the General tab in the Additional settings pane.
Type the new file extension in either the VHDL file extension or Verilog file extension field. The field for the language you have not selected is disabled.

This figure shows how to specify an alternate file extension for VHDL files. The coder generates the filter file MyFIR.vhdl.

Generate HDL tool

Note

When specifying character vectors for file names and file type extensions, consider platform-specific requirements and restrictions. Also consider postfix character vectors that the coder appends to the Name, such as '_tb' and'_pkg'.

Set HDL File Name Extensions Via the Command-Line

Command-Line Alternative: Use the generatehdl function with the Name property to set the name of your filter entity and the base character vector for generated HDL file names. To specify an alternative file type extension for generated files, call the function with the VerilogFileExtension or VHDLFileExtension property.

Splitting Entity and Architecture Code Into Separate Files

By default, the coder includes a VHDL entity and architecture code in the same generated VHDL file. Alternatively, you can instruct the coder to place the entity and architecture code in separate files. For example, instead of generated code residing in MyFIR.vhd, you can specify that the code reside in MyFIR_entity.vhd and MyFIR_arch.vhd.

The names of the entity and architecture files derive from:

The base file name, as specified by the Name field in the Target pane of the Generate HDL tool.
Default postfix values '_entity' and '_arch'.
The VHDL file type extension, as specified by the VHDL file extension field on the General pane of the Generate HDL tool.

To split the filter source file, do these steps.

Select the Global Settings tab on the Generate HDL tool.
Select the General tab in the Additional settings pane.
Select Split entity and architecture. The Split entity file postfix and Split arch. file postfix fields are now enabled.
Specify new character vectors in the postfix fields if you want to use postfixes other than '_entity' and '_arch' to identify the generated VHDL files.
Note
When specifying a character vector for use as a postfix value in file names, consider the size of the base name and platform-specific file naming requirements and restrictions.

Command-Line Alternative: Use the generatehdl function with the property SplitEntityArch to split the VHDL code into separate files. To modify the file name postfix for the separate entity and architecture files, use the SplitEntityFilePostfix and SplitArchFilePostfix properties.