Design and analyze SerDes systems for export to Simulink, MATLAB and IBIS-AMI
The SerDes Designer app generates the SerDes Designer tree required to generate IBIS-AMI models. Start from the app to develop initial SerDes architecture using statistical analysis and manage developed models.
Using this app, you can:
Create fully compliant IBIS(Input/Output Buffer Information Specification)-AMI(Algorithmic Modeling Interface) models and perform statistical analysis.
Generate MATLAB scripts for further customization and statistical and time domain analysis.
Export Simulink® models for further customization, statistical and time domain analysis, and IBIS-AMI model generation.
To know more about this app, see Design SerDes System and Export IBIS-AMI Model.
Open the SerDes Designer App
MATLAB® Toolstrip: In the Apps tab, under Signal Processing and Communications, click the app icon.
MATLAB command prompt: Enter
serdesDesigner opens a new session of the SerDes
Designer app, enabling you to design and analyze a SerDes system.
serdesDesigner(serdesDesign) opens the SerDes Designer
app and loads the
serdesDesign file saved from the previous
IBIS-AMI codegen is not supported in MAC.
Configuring SerDes System
The SerDes Designer app provides built-in configuration settings for customizing your SerDes system. From the app toolstrip, go to Configuration tab, and select relevant settings.
|Symbol Time (ps)
|Samples per Symbol
Setting Up Transmitter and Receiver
Configuring Analog Channel
Use the Channel block to set up the model of the analog channel. The Channel block constructs a loss model using a channel loss metric or an impulse response.
You can also introduce crosstalk in your simulations. You can specify the maximum
allowed crosstalk for specifications such as
CEI-28G-VSR. Or you can specify a custom integrated crosstalk
noise (ICN) level.
From the SerDes Designer app toolstrip, go to Analysis tab and select Add Plots to perform statistical (Init) analysis. By default, the app selects the Auto-Analyze button and automatically updates the plot results every time you make a change in the SerDes system. To update the plot at your preference, clear the Auto-Analyze button and update the plot by clicking the Analyze button.
You can view these plots using the app:
PRBS (pseudorandom binary sequence) Waveform
BER (bit error rate)
CTLE Transfer Function
You can also view important performance metrics of the SerDes system by selecting Report on the Add Plots tab.
|Eye Height (V)
|Eye height at the center of the BER contour
|Eye Width (ps)
|Eye width of the BER contour
|Eye Area (V*ps)
|Area inside the BER contour eye
|Measure of the variance of amplitude separation among different levels of PAMn, given by the equation:
|Channel operating margin, given by the equation:
|Vertical eye closure, given by the equation:
In a PAMn modulation, there are (n-1) inner eyes. Each eye generates its own COM and VEC values. The app reports the minimum of the generated COM values and the maximum of the generated VEC values.
According to IBIS BIRD (Buffer Issue Resolution Document) 213, IBIS-AMI models support any level of signaling from PAM2 (NRZ) to upwards, collectively known as PAMn. If your EDA tool supports it, you can export IBIS-AMI models supporting modulation schemes NRZ, PAM3, PAM4, PAM8, or PAM16.
You can include jitter impairment in analysis during link and equalization design. This helps you perform trade-off between different equalization schemes which have different contributions to the total jitter. You can also calculate eye margin during link analysis and include jitter values in the IBIS-AMI models.
From the app, you can define the clock mode, transmitter jitter parameters, and receiver jitter parameters. The clock probability density function (PDF) is included on the BER plot. For more information about jitter parameters, see Jitter Analysis in SerDes Systems.
If you export your SerDes model to Simulink, the jitter values set in the app are used to populate the SerDes IBIS-AMI tree.
Exporting SerDes System
From the app toolstrip, go to Export tab. You can either:
Export SerDes System to Simulink
Generate MATLAB Code for SerDes System
Make IBIS-AMI Model for SerDes System
The Simulink model of the SerDes system contains a Configuration block that contains the system level settings, a Stimulus block to use in time-domain simulation and an Eye Diagram Scope to view the statistical eye.
The Tx and Rx blocks are automatically generated by the SerDes Designer app. The equalization blocks are placed inside them to allow IBIS-AMI model generation.
Import S-Parameters for Channel Model
If you set your Channel model as
response, you can import S-Parameters from a Touchstone file to use as your channel model by clicking the Import
S-Parameter model. From the S-Parameter Fitter dialog box that opens, you can
set the maximum number of poles, error tolerance, transmitter amplitude, rise time and RTF
factor, and the resistor and capacitor values. You can also plot the impulse response before
selecting it for channel model.
Select Clock Recovery Model
To successfully send and receive data between a SerDes transmitter and receiver, you need to ensure that the receiver samples the voltage waveform at the correct time instants to recover the message. Typically, the transmitter and receiver have independent oscillators which set the operating frequency of the system within a specified tolerance of each other. But the receiver still needs to recover the clock phase and frequency from the waveform signal itself. A clock and data recovery function is accomplished by utilizing a phase detector algorithm and filtering the phase error information to recover the signal phase and frequency.
You can select which phase detector model the app uses in the clock recovery: bang-bang (Alexander) or baud-rate type-A (Mueller-Muller) using the CDR or DFECDR block.
The bang-bang phase detector is typically found in analog-based SerDes systems. In these systems, an edge of the eye sampler and a data sampler at the middle of the eye are used together to determine if the data sample is early or late. A sampler circuit that can determine if the input voltage is greater than or less than a voltage threshold.
The baud-rate type-A phase detector is found in ADC-based SerDes systems. In these systems, the voltage sample, determined with several bits of precision, and the resolved symbol is used to determine if the sample is early or late.
Extended Support with Other Compilers and Products
If you have Simulink license, you can export Simulink and IBIS-AMI models from the app.
If you have a supported compiler, you can compile the SerDes system in that compiler from the app. For a list of supported compilers, see Supported and Compatible Compilers.
If you have a license for Simulink Coder™ or Embedded Coder®, you can keep your C files during .dll file generation. Otherwise, your C files will be deleted during the .dll file generation.
To learn about compatibility issues on different Linux platforms, see Linux Version Compatibilities.
Introduced in R2019a