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Serial Link Design

Design high speed serial links such as PCIe, USB, and Ethernet

The Serial Link Designer app provides a dedicated system-level design and analysis environment for multi-gigabit serial links. Capture your serial link designs graphically and experiment with different physical layout and equalization strategies to predict how design alternatives affect operating margins and the bit error rate (BER) of the link. Use network characterization to model the behavior of the unequalized analog network. This enables quick evaluation of the analog channel design for different trade-offs. Predict the end-to-end behavior of the link using SerDes equalization techniques and clock recovery models obtained by statistical and time-domain analysis. Determine the effect of aggressor signals on overall BER of the channel using crosstalk analysis.

Use the Serial Link Designer app to configure high speed serial links. Set simulation parameters, specify corner conditions, and define stimulus patterns. Set up pre-layout analysis to run SPICE, network characterization, statistical and time domain simulations to analyze your custom serial links. View and interpret the results using the Signal Integrity Viewer app. You can also set up and analyze the post-layout PCB database of your serial link design if you have a license for RF PCB Toolbox™. You can modify the stackup and padstack models and customize vias and see how the changes impact your design.


Serial Link DesignerAnalyze PCB designs for serial link applications
Signal Integrity ViewerView the signal integrity results of Serial Link Designer or Parallel Link Designer app


Serial Link Design Basics

Configure Serial Link Projects

Pre-Layout Analysis

Post-Layout Verification (Requires RF PCB Toolbox)

Results to View with Signal Integrity Viewer