RF e segnale misto

Modellare e simulare sistemi RF, SerDes e a segnale misto

È possibile utilizzare i seguenti prodotti Simulink^® per modellare e simulare sistemi a radiofrequenza (RF), serializzatori/deserializzatori (SerDes) e a segnale misto con maggiore velocità e accuratezza.

RF Blockset consente di modellare elementi a RF e simulare ricetrasmettitori e terminali a RF a diversi livelli di astrazione. È possibile caratterizzare i modelli a RF per modellare architetture adattive, tra cui AGC, algoritmi DPD e beamforming. RF Blockset consente inoltre di nascondere i dettagli di implementazione del modello.
SerDes Toolbox consente di modellare sistemi SerDes e di generare modelli IBIS-AMI per interconnessioni digitali ad alta velocità. È possibile osservare gli effetti di ISI, jitter, rumore, perdita di inserzione e diafonia nonché verificare la conformità dei canali agli standard industriali, come IEEE 802.3, OIF, PCle, USB e DDR5.
Mixed-Signal Blockset consente di modellare sistemi ADC, DAC, PLL e SMPS. È inoltre possibile verificare circuiti integrati a segnale misto e combinare i comportamenti dei circuiti analogici con i modelli digitali per creare rappresentazioni più dettagliate dei sistemi elettronici.

Argomenti

Getting Started with RF Modeling (RF Blockset)
Build a simple RF receiver and perform circuit envelope simulation.
Design SerDes System and Export IBIS-AMI Model (SerDes Toolbox)
Create and analyze a SerDes system, and export an IBIS-AMI model using the SerDes Designer app.
Design and Evaluate Simple PLL Model (Mixed-Signal Blockset)
This example shows how to design a simple phase-locked loop (PLL) using a reference architecture and validate it using PLL Testbench.

Esempi in primo piano

Top-Down Design of RF Receiver

Design an RF receiver for a ZigBee-like application using a top-down methodology.

Power Amplifier and DPD Modeling for Dynamic EVM Measurement

Extract a PA model using measured data, verify the quality of the fitting, and simulate the PA model with and without DPD.

Enable Model Protection and Accelerator Modes in RF Blockset Models

Conceal implementation details and enable accelerator modes in your RF Blockset model.

Architectural 112G PAM4 ADC-Based SerDes Model

Model a 112G PAM4 time-interleaved ADC-Based SerDes.

PCIe6 Transmitter/Receiver IBIS-AMI Model

Create IBIS-AMI models for a PCI-Express Generation 6 (PCIe Gen6) transmitter and receiver using the library blocks in SerDes Toolbox™. The IBIS-AMI models generated by this example can be used in Serial Link Designer from Signal Integrity Toolbox™ and conform to the PCIe Gen6 Base-Specification published by the PCI-SIG.

USB4 V2 Transmitter/Receiver IBIS-AMI Model

Implement USB4 V2 (80Gbps PAM3) Transmitter and Receiver architectures with SerDes Designer and generate IBIS-AMI models using the library blocks in SerDes Toolbox™. The generated models conform to the IBIS-AMI and USB4 V2 specifications.

Design and Evaluate Successive Approximation ADC Using Stateflow

Design and evaluate a 12-bit successive approximation register ADC.

Boost Power Train Design Workflow

Design a power supply with a boost power train for a specific operating point, control the output voltage, and perform time-domain simulations.

Digital Phase Locked Loop

Model a digital phase locked loop using the Mixed-Signal Blockset™. In a digital phase locked loop, phase detection is performed by a time to digital converter (TDC), loop filtering is performed by a digital filter, and the oscillator is a digitally controlled oscillator (DCO). This example demonstrates a behavioral model of a TDC, using the BiquadFilter from the DSP System Toolbox™ as the digital loop filter, and using VCOs and DACs from the Mixed-Signal Blockset to model the DCO.