Neighborhood Processing Subsystem

Create algorithm that follows the neighborhood pattern

Since R2022b

• 

Libraries:
Simulink / Matrix Operations

Description

The Neighborhood Processing Subsystem block is a Subsystem block preconfigured as a starting point for creating a subsystem that follows the neighborhood pattern. At each simulation time step, the subsystem iterates over each element of an input array. For each element, the subsystem processes a neighborhood of values surrounding that element. Use the subsystem for image processing. Certain image processing algorithms involve processing images in sections rather than processing the entire image at once.

Configuring Subsystem

The Neighborhood Processing Subsystem contains a Neighborhood block that acts as a control block for the subsystem. Specify the parameters of the Neighborhood block to configure the behavior of the subsystem.

The Neighborhood size parameter controls the dimensions of the neighborhood. For elements near the edges of the input matrix, the neighborhood can extend beyond the input matrix. The Padding option parameter controls how the subsystem treats values from outside the input matrix. You can configure the subsystem to pad these values with a constant or by reusing values from inside the matrix. If you use the Constant padding option, use the Padding constant parameter to set the constant value.

You can configure the Neighborhood Processing Subsystem block to process only certain elements of an input matrix. Use the Stride parameter to configure the Neighborhood Processing Subsystem block to skip a certain number of elements at each iteration. Use the Processing offset and Processing width parameters to define the top left and bottom right boundaries, respectively, of a region of interest (ROI) within the image. The Neighborhood Processing Subsystem block iterates over only that region.

The Output size parameter controls the size of the output matrix. The Same value configures the output matrix to be the same size as the ROI. The Full value produces a larger output matrix by calculating values for elements outside the ROI whose neighborhoods include at least one element from the ROI. The Valid value creates a smaller output matrix by calculating values for only the elements whose neighborhoods do not extend beyond the ROI. When you use this setting, the Padding constant parameter is disabled.

Example

Consider this model.

In this example, the Neighborhood Processing Subsystem block takes a 5-by-5 matrix and outputs a matrix of the same dimensions by using the Same output size option. The subsystem contains these blocks.

Inside the Neighborhood Processing Subsystem block, the inport does not receive the full 5-by-5 matrix. Instead, because the Neighborhood size parameter value is [3 3], the inport receives a smaller, 3-by-3 window of elements. The subsystem iterates over the elements of the input matrix, passing the neighborhood of each element to the inport at each iteration.

The model uses the Constant padding option with a padding value of 0. For neighborhoods that extend beyond the input matrix, the subsystem treats the external values as 0.

The outport of the Neighborhood Processing Subsystem block receives a scalar which represents the derived value for the element at the center of the window. In this case, a Sum of Elements block with the Sum over parameter set to All dimensions produces a scalar for each window, representing the sum of the values in that window.

Run the model to populate the Display block.

Each value of the output matrix is the sum of the corresponding element and its eight direct neighbors in the input matrix. The inner elements are surrounded by values of 1, and so have the value 9. The outer elements have lower values because the selected padding method uses the value 0 for elements outside the input matrix.

Examples

Calculate Optical Flow by Using Neighborhood Processing Subsystem Blocks

Use Neighborhood Processing Subsystem blocks to calculate the apparent motion of objects in a video.

Open Live Script

Perform Edge Detection by Using a Neighborhood Processing Subsystem Block

Use a Neighborhood Processing Subsystem block to detect edges in an image.

Open Live Script

Perform Corner Detection by Using Neighborhood Processing Subsystem Blocks

Use Neighborhood Processing Subsystem blocks to detect corners in an image.

Open Live Script

Perform Fog Rectification by Using Neighborhood Processing Subsystem Blocks

Use Neighborhood Processing Subsystem blocks to remove fog from an image.

Open Live Script

Convert RGB Image to Grayscale by Using a Neighborhood Processing Subsystem Block

Use a Neighborhood Processing Subsystem block to convert a color image to grayscale.

Open Live Script

Limitations

• The Neighborhood Processing Subsystem block does not support Switch blocks when you use normal simulation mode. To use a Switch block inside a Neighborhood Processing Subsystem block, use the accelerator or rapid accelerator simulation mode. For a workaround in normal simulation mode, see the Tips section.

• The Neighborhood Processing Subsystem block does not support row-major layout.

Ports

Input

In — Signal input to a subsystem

matrix

Use Inport blocks to get signals from the local environment.

Placing an Inport block in a Neighborhood Processing Subsystem block adds an external input port to the subsystem. The port label matches the name of the Inport block. Use the Neighborhood control block to configure which input signals to process using the neighborhood pattern.

Data Types: single | double | int8 | int16 | int32 | int64 | uint8 | uint16 | uint32 | uint64 | fixed point

Output

Out — Signal output from a subsystem

matrix

Use Outport blocks to send signals to the local environment.

Placing an Outport block in a Neighborhood Processing Subsystem block adds an external output port from the subsystem. The port label matches the name of the Outport block.

Data Types: single | double | int8 | int16 | int32 | int64 | uint8 | uint16 | uint32 | uint64 | fixed point

Block Characteristics

Data Types	double | fixed point | integer | single
Direct Feedthrough	no
Multidimensional Signals	yes
Variable-Size Signals	no
Zero-Crossing Detection	no

Tips

• To improve performance, consider setting the Measure function execution times (Embedded Coder) configuration parameter to Coarse (referenced models and subsystems only) when you run software-in-the-loop (SIL) or processor-in-the-loop (PIL) profiling on a model that contains a Neighborhood Processing Subsystem block. Neighborhood Processing Subsystem blocks process large amounts of data, which can cause poor performance when you use the Detailed (all function call sites) option. For more information, see Create Execution-Time Profile for Generated Code (Embedded Coder).

• Switch blocks are useful in Neighborhood Processing Subsystem blocks for image processing tasks such as thresholding. Thresholding can convert an image to black and white by converting every pixel value to 255 or 0, depending on whether the input pixel value is greater than a given threshold value. For example, this Neighborhood Processing Subsystem block performs thresholding by using a Switch block with a threshold value of 110.

  

  To perform thresholding in normal simulation mode, consider using a Relational Operator block that uses the > operator to recreate the Switch block behavior.

  

  The Relational Operator block returns a value of 1 if the input value is greater than the threshold and otherwise returns 0. By sending this value to a Gain block with a value of 255, the subsystem returns 255 or 0.

Extended Capabilities

C/C++ Code Generation
Generate C and C++ code using Simulink® Coder™.

HDL Code Generation

Generate Verilog and VHDL code for FPGA and ASIC designs using HDL Coder™.

HDL Coder™ provides additional configuration options that affect HDL implementation and synthesized logic.

HDL Architecture

Architecture	Description
Module (default)	Generate code for the subsystem and the blocks within the subsystem.
BlackBox	Generate a black box interface. The generated HDL code includes only the input/output port definitions for the subsystem. Therefore, you can use a subsystem in your model to generate an interface to existing, manually written HDL code. The black-box interface generation for subsystems is similar to the Model block interface generation without the clock signals.
No HDL	Remove the subsystem from the generated code. You can use the subsystem in simulation, however, treat it as a “no-op” in the HDL code.

Black Box Interface Customization

For the BlackBox architecture, you can customize port names and set attributes of the external component interface. See Customize Black Box or HDL Cosimulation Interface (HDL Coder).

HDL Block Properties

General
AdaptivePipelining	Automatic pipeline insertion based on the synthesis tool, target frequency, and multiplier word-lengths. The default is inherit. See also AdaptivePipelining (HDL Coder).
BalanceDelays	Detects introduction of new delays along one path and inserts matching delays on the other paths. The default is inherit. See also BalanceDelays (HDL Coder).
ClockRatePipelining	Insert pipeline registers at a faster clock rate instead of the slower data rate. The default is inherit. See also ClockRatePipelining (HDL Coder).
ConstrainedOutputPipeline	Number of registers to place at the outputs by moving existing delays within your design. Distributed pipelining does not redistribute these registers. The default is 0. For more details, see ConstrainedOutputPipeline (HDL Coder).
DistributedPipelining	Pipeline register distribution, or register retiming. The default is inherit. See also DistributedPipelining (HDL Coder).
DSPStyle	Synthesis attributes for multiplier mapping. The default is none. See also DSPStyle (HDL Coder).
FlattenHierarchy	Remove subsystem hierarchy from generated HDL code. The default is inherit. See also FlattenHierarchy (HDL Coder).
InputPipeline	Number of input pipeline stages to insert in the generated code. Distributed pipelining and constrained output pipelining can move these registers. The default is 0. For more details, see InputPipeline (HDL Coder).
OutputPipeline	Number of output pipeline stages to insert in the generated code. Distributed pipelining and constrained output pipelining can move these registers. The default is 0. For more details, see OutputPipeline (HDL Coder).
SharingFactor	Number of functionally equivalent resources to map to a single shared resource. The default is 0. See also Resource Sharing (HDL Coder).
StreamingFactor	Number of parallel data paths, or vectors, that are time multiplexed to transform into serial, scalar data paths. The default is 0, which implements fully parallel data paths. See also Streaming (HDL Coder).

If this block is not the DUT, the block property settings in the Target Specification tab are ignored. In the HDL Workflow Advisor, if you use the IP Core Generation workflow, these target specification block property values are saved with the model. If you specify these target specification block property values using hdlset_param, when you open HDL Workflow Advisor, the fields are populated with the corresponding values.

Target Specification
AdditionalTargetInterfaces	Additional target interfaces, specified as a character vector. To save this block property on the model, in the Set Target Interface task of the IP Core Generation workflow, corresponding to the DUT ports that you want to add more interfaces, select Add more.... You can then add more interfaces in the Add New Target Interfaces dialog box. Specify the type of interface, number of additional interfaces, and a unique name for each additional interface. Values: '' (default) | cell array of character vectors Example: '{{'AXI4-Stream','InterfaceID','AXI4-Stream1'}}'
ProcessorFPGASynchronization	Processor/FPGA synchronization mode, specified as a character vector. To save this block property on the model, specify the Processor/FPGA Synchronization in the Set Target Interface task of the IP Core Generation workflow. Values: Free running (default) | Coprocessing - blocking Example: 'Free running'
TestPointMapping	To save this block property on the model, specify the mapping of test point ports to target platform interfaces in the Set Target Interface task of the IP Core Generation workflow. Values: '' (default) | cell array of character vectors Example: '{{'TestPoint','AXI4-Lite','x"108"'}}'
TunableParameterMapping	To save this block property on the model, specify the mapping of tunable parameter ports to target platform interfaces in the Set Target Interface task of the IP Core Generation workflow. Values: '' (default) | cell array of character vectors Example: '{{'myParam','AXI4-Lite','x"108"'}}'
AXI4RegisterReadback	To save this block property on the model, specify whether you want to enable readback on AXI4 subordinate write registers in the Generate RTL Code and IP Core task of the IP Core Generation workflow. To learn more, see Model Design for AXI4 Slave Interface Generation (HDL Coder). Values: 'off' (default) | 'on'
AXI4SlaveIDWidth	To save this block property on the model, specify the number of AXI manager interfaces that you want to connect the DUT IP core to by using the AXI4 Slave ID Width setting in the Generate RTL Code and IP Core task of the IP Core Generation workflow. To learn more, see Define Multiple AXI Master Interfaces in Reference Designs to Access DUT AXI4 Slave Interface (HDL Coder). Values: 'off' (default) | 'on'
AXI4SlavePortToPipelineRegisterRatio	To save this block property on the model, specify the number of AXI4 subordinate ports for which you want a pipeline register to be inserted by using the AXI4 Slave port to pipeline register ratio setting in the Generate RTL Code and IP Core task of the IP Core Generation workflow. To learn more, see Model Design for AXI4 Slave Interface Generation (HDL Coder). Values: 'off' (default) | 'on''10''20''35''50'
GenerateDefaultAXI4Slave	To save this block property on the model, specify whether you want to disable generation of default AXI4 subordinate interfaces in the Generate RTL Code and IP Core task of the IP Core Generation workflow. Values: 'on' (default) | 'off'
IPCoreAdditionalFiles	Verilog® or VHDL® files for black boxes in your design. Specify the full path to each file, and separate file names with a semicolon (;). You can set this property in the HDL Workflow Advisor, in the Additional source files field. Values: '' (default) | character vector Example: 'C:\myprojfiles\led_blinking_file1.vhd;C:\myprojfiles\led_blinking_file2.vhd;'
IPCoreName	IP core name, specified as a character vector. You can set this property in the HDL Workflow Advisor, in the IP core name field. If this property is set to the default value, the HDL Workflow Advisor constructs the IP core name based on the name of the DUT. Values: '' (default) | character vector Example: 'my_model_name'
IPCoreVersion	IP core version number, specified as a character vector. You can set this property in the HDL Workflow Advisor, in the IP core version field. If this property is set to the default value, the HDL Workflow Advisor sets the IP core version. Values: '' (default) | character vector Example: '1.3'
IPDataCaptureBufferSize	FPGA Data Capture buffer size, specified as a character vector. Use FPGA Data Capture to observe signals in a design when running on an FPGA. The buffer size uses values that are 128*2^n, where n is an integer. By default, the buffer size is 128 (n=0). The maximum value of n is 13, which means that the maximum value for buffer size is 1048576 (=128*2^13). Values: '' (default) | character vector Example: '1.3'

Restrictions

If your DUT is a masked subsystem, you can generate code only if it is at the top level of the model.

For more information, see:

• External Component Interfaces (HDL Coder)

• Generate Black Box Interface for Subsystem (HDL Coder)

Version History

Introduced in R2022b