Write data to a register region on the specified IP core
SoC Blockset / Processor I/O
The Register Write block writes data from your processor algorithm to a register region on the specified IP core. In simulation, a timer-driven or event-driven task subsystem contains the Register Write block. The data signals from the Register Write block connect to the Register Channel block managing those registers and their transactions.
When developing or analyzing the software side of an SoC application, the Register Write block can be connected to an IO Data Sink block. In this configuration, the IO Data Sink block provides either previously recorded or artificial data, enabling a more directed simulation of the software and processor side of the application, without need to explicitly model the hardware and memory interactions.
data— Data input
This port receives the data vector to write to the registers on the IP core starting at Offset address from the base address of the IP core.
Output sink— Direct output to port or base workspace
To output port(default) |
To output port to write data to the output port,
Base workspace to write data to a
variable in the base workspace. When writing to the base workspace, the block updates
the value of a
Simulink.Parameter object with name set
Simulink.Parameter object name parameter in the base
Placing the Register Write block inside a Initialize Function block subsystem, writes to a
Simulink.Parameter object at the start of simulation. A register,
represented as a Constant block, in an FPGA reference
model can be initialized at the start of simulation with the value of the
Simulink.Parameter object. This method of writing to FPGA registers
requires a constant value throughout the simulation but can reduce the simulation time
required by your SoC model.
Simulink.Parameter object name— Name of Simulink.Parameter object
A(default) | character vector
Simulink.Parameter object to be created
Device name— Path and file name of IP core device
/dev/mwipcore(default) | character array
Enter the path and file name of the IP core device.
Offset address— Offset from the base address of the IP core to the register
hex2dec('0100')(default) | positive integer
To automatically generate C code for your design, and execute on an SoC device, use the SoC Builder tool. See Generate SoC Design. You must have an Embedded Coder® license to generate and execute C code for your SoC device.
SoC Builder implements the Register Write block with FPGA and processor IPs that use the AXI4 interface protocol. The AXI4 interface protocol allows the processor to write vector data from the processor to a contiguous group of registers on the FPGA. Use this block for simple, low-throughput memory-mapped communication, such as writing to control and status registers. This diagram shows a generalized representation of the generated code implementation.