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Video Capture USB

Import live video frames from one or more USB cameras on Zynq-based hardware

Since R2024b

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Add-On Required: This feature requires the SoC Blockset Support Package for AMD FPGA and SoC Devices add-on.

  • Video Capture USB block

Libraries:
SoC Blockset Support Package for AMD FPGA and SoC Devices / MPSoC / ZCU106

Description

The Video Capture USB block captures video frames from a Zynq®-based board that has one or more USB video device class (UVC) cameras, and imports the frames into your Simulink® model. The reference design programs the FPGA with an image that includes a USB 3.0 camera interface, data path multiplexers, video format conversions, and a video test pattern generator (TPG). You can control these data path and conversion options from the Video Capture USB block.

Limitations

  • To use this block, in the hardware setup, set Hardware Board to Xilinx Zynq UltraScale+ MPSoC ZCU106 Evaluation Kit and set Add-on Card to USB Camera.

  • Use the IP core workflow to generate HDL code. This block does not support using the SoC Builder tool. For more information on workflows, see SoC Generation Workflows.

    In the HDL Workflow Advisor tool, in step 1.1, set Target platform to Xilinx Zynq UltraScale+ MPSoC ZCU106 Evaluation Kit. In step 1.2, set Reference design to USB Camera Receive Path.

Ports

Output

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The block returns one matrix for each color component of the input video. The dimensions of the Y matrix match the frame size. The dimensions of the Cb and Cr matrices are height-by-width/2 because the 4:2:2 format alternates Cb and Cr values for each pixel in the frame.

Dependencies

To enable these ports, set Pixel format to YCbCr 4:2:2.

Data Types: single | double | int8 | int16 | int32 | int64 | uint8 | uint16 | uint32 | uint64 | Boolean | fixed point

The block returns one matrix for each color component of the input video. The dimensions of each matrix match the frame size.

Dependencies

To enable these ports, set Pixel format to RGB and Image signal to Separate color signals.

Data Types: single | double | int8 | int16 | int32 | int64 | uint8 | uint16 | uint32 | uint64 | Boolean | fixed point

The block returns a 3-by-height-by-width matrix, where height and width match the frame size.

Dependencies

To enable this port, set Pixel format to RGB and Image signal to One multidimensional signal.

Data Types: single | double | int8 | int16 | int32 | int64 | uint8 | uint16 | uint32 | uint64 | Boolean | fixed point

Parameters

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Ethernet address of an SoC device connected to your host machine.

The video stream through the FPGA logic and ARM® processor can start with input video from the USB port of the SoC device or with generated video from the test pattern generator (TPG). Use the Scan button to detect one or more cameras connected to the USB port of your SoC device. The drop-down menu updates with the names of the detected cameras.

  • detected camera name — Camera connected to the USB input port on the SoC device. The Frame size parameter menu updates to match the available resolutions from the detected camera.

  • Test pattern generator — On-chip TPG. The TPG creates input frames at the requested resolution. Select a fixed color bar pattern or a moving ball in the Test pattern parameter. When you select the TPG, you do not need a camera connected to the USB port on the SoC device.

The test pattern generator creates input frames at the requested resolution.

  • SMPTE color bars —

    Color bar test pattern captured when you set Test pattern to SMPTE color bars.

  • Moving ball —

    Color bar test pattern captured when you set Test pattern to Moving ball.

Select from the supported resolutions available on your detected camera.

To use a frame size greater than 2k resolution, you must configure the FPGA reference design to use 2-pixel-per-clock streaming. The default reference design loaded during setup uses 2-pixel-per-clock streaming. You can configure the number of pixels per clock in Step 1.2 of the HDL Workflow Advisor. For details, see Target FPGA on Zynq Hardware.

For the test pattern generator, these resolutions are available:

  • 320x240p

  • 640x480p

  • 1280x720p

  • 1920x1080p

The block calculates available frame rates based on the supported resolutions available from the detected camera.

The block sets the Simulink sample time for the captured video frames to 1/Frame rate.

Specify the format of the pixel stream as one of these values.

  • RGB — Three 8 bit color components per pixel, which is 24 bits per pixel total.

  • YCbCr 4:2:2 (default) — Also known as YUYV. An 8 bit Y component and an interleaved 8 bit CbCr component. The effective pixel size is 16 bits. The block returns the component frames on the Y, Cb, and Cr output ports.

Specify the format of the pixel stream as one of these values.

  • RGB — Three 8 bit color components per pixel, which is 24 bits per pixel total.

  • YCbCr 4:2:2 (default) — Also known as YUYV. An 8 bit Y component and an interleaved 8 bit CbCr component. The effective pixel size is 16 bits. The block returns the component frames on the Y, Cb, and Cr output ports.

Select this parameter to bypass the user logic section of the FPGA and send the input video frames directly to the host.

Specify the RGB output stream format as one of these values.

  • Separate color signals — The block returns separate height-by-width matrices for each color component. In this case, the block has R, G, and B output ports.

  • One multidimensional signal — The block returns a single 3-by-height-by-width matrix. In this case, the block has an Image output port.

Dependencies

To enable this parameter, set Pixel format to RGB.

Version History

Introduced in R2024b

See Also

Blocks