Generate HDL code for fixed-point filters

Filter Design HDL Coder™ generates synthesizable, portable VHDL® and Verilog® code for implementing fixed-point filters designed with MATLAB® on FPGAs or ASICs. It automatically creates VHDL and Verilog test benches for simulating, testing, and verifying the generated code.


Working with Filter Design HDL Coder

Design filters and generate VHDL and Verilog code.

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Designing Fixed-Point Filters

Create a quantized filter, which is the design entry input to the toolbox.

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Generating HDL for Fixed-Point Filters

Generate VHDL or Verilog code for fixed-point filters.

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Customizing VHDL and Verilog Code

Generate filter and test bench HDL code for a quantized filters.

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Testing and Synthesizing Generated HDL Code

Create a VHDL or Verilog test bench to simulate and test HDL code.

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Product Requirements

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