Filtri in virgola fissa
R2024aÈ possibile modellare gli algoritmi di filtraggio dell'elaborazione del segnale in virgola fissa e analizzare gli effetti della quantizzazione sul comportamento e sulle prestazioni del sistema utilizzando le funzionalità DSP System Toolbox™ e Fixed-Point Designer™. Per un elenco dei System object DSP System Toolbox che supportano le operazioni in virgola fissa, vedere System Objects in DSP System Toolbox that Support Fixed-Point Design. Per un elenco dei blocchi di DSP System Toolbox che supportano le operazioni in virgola fissa, utilizzare la funzione showsignalblockdatatypetable.
Oggetti
Funzioni
freqrespest | Frequency response estimate via filtering |
freqrespopts | Create an options object for frequency response estimate |
freqz | Frequency response of discrete-time filter System object |
impz | Impulse response of discrete-time filter System object |
isstable | Verify that discrete-time filter System object is stable |
noisepsd | Power spectral density of filter output due to round-off noise |
noisepsdopts | Create an options object for output noise PSD computation |
reorder | Reorder second-order sections of biquadratic filter System object |
scale | Scale second-order sections |
specifyall | Fully specify fixed-point filter System object settings |
zplane | Z-plane zero-pole plot for discrete-time filter System object |
Blocchi
 | Allpole Filter | Model allpole filters |
 | Biquad Filter | (To be removed) Model biquadratic IIR (SOS) filters |
 | Differentiator Filter | Direct form FIR fullband differentiator filter |
 | Discrete Filter | Model Infinite Impulse Response (IIR) filters |
 | Discrete FIR Filter | Model FIR filters |
 | Highpass Filter | Design FIR or IIR highpass filter |
 | Lowpass Filter | Design FIR or IIR lowpass filter |
 | CIC Compensation Decimator | Compensate for CIC filter using FIR decimator |
 | CIC Compensation Interpolator | Compensate for CIC filter using FIR interpolator |
 | CIC Decimation | Decimate signal using cascaded integrator-comb filter |
 | CIC Interpolation | Interpolate signal using cascaded integrator-comb filter |
 | Digital Down-Converter | Translate digital signal from intermediate frequency (IF) band to baseband and decimate it |
 | Digital Up-Converter | Interpolate and translate digital signal from baseband to intermediate frequency (IF) band |
 | Farrow Rate Converter | Polynomial sample-rate converter with arbitrary conversion factor |
 | FIR Decimation | Perform polyphase FIR decimation |
 | FIR Halfband Decimator | Decimate signal using polyphase FIR halfband filter |
 | FIR Halfband Interpolator | Interpolate signal using polyphase FIR halfband filter |
 | FIR Interpolation | Perform polyphase FIR interpolation |
 | FIR Rate Conversion | Perform polyphase FIR sample rate conversion |
 | Two-Channel Analysis Subband Filter | Decompose signal into high-frequency and low-frequency subbands |
| Two-Channel Analysis Subband Filter | Decompose signal into high-frequency and low-frequency subbands |
 | LMS Filter | Compute output, error, and weights using least mean squares (LMS) adaptive algorithm |
| Filter Realization Wizard |
Argomenti
- Fixed-Point Precision Rules for Avoiding Overflow in FIR Filters
Precision Rules for Avoiding Overflow in FIR Filters.
- Create an FIR Filter Using Integer Coefficients
Learn how to create an FIR filter using integer coefficients.
- Fixed-Point Filter Design in MATLAB
Design filters for use with fixed-point input.
Esempi in primo piano
Sigma-Delta A/D Conversion
Model analog-to-digital conversion by implementing a sigma-delta algorithm.
Cochlear Implant Speech Processor
Simulate the design of a cochlear implant that can be placed in the inner ear of a profoundly deaf person to restore partial hearing. Signal processing is used in cochlear implant development to convert sound to electrical pulses. The pulses can bypass the damaged parts of a deaf person's ear and be transmitted to the brain to provide partial hearing.
Design and Analysis of a Digital Down Converter
Use the digital down converter (DDC) System object™ to emulate the TI Graychip 4016 digital down converter in a simple manner. We base the example on a comparison with the GSM Digital Down Converter in Simulink example. We show how the DDC System object can be used to design and analyze the decimation filters and to quickly explore different design options that meet various passband and stopband frequency and attenuation specifications. This example requires a Fixed-Point Designer™ license.
