Deploy Motor Control Algorithms to FPGAs – Getting Started
From the series: Deploying Motor Control Algorithms to an FPGA
Learn how to deploy your Simulink® model to the FPGA fabric on a system-on-chip (SoC) for Field Oriented Control (FOC) of a Permanent Magnet Synchronous Machine (PMSM). We will highlight how:
- The Simulink and Embedded Coder® workflow can be extended to generate HDL code with HDL Coder™.
- HDL Coder generates device-independent native floating-point operations and fixed-point operations.
- The generated HDL code is readable, optimized, and traceable back to the Simulink model.
In this video we will focus on the steps to deploy motor control algorithms to FPGA. We will show the workflow for the generation of the HDL Code from the Simulink model for the Field Oriented Control of a Permanent Magnet Synchronous machine.
In this Simulink model, the control of the PMSM is done by regulating the phase current to control torque. The encoder is designed to capture the dynamics at 25kHz from the sensor, but in real world the encoder must process the input in the mega-hertz region for incoming pulses. This requires achieving encoder sensor calibration before the controller can achieve closed loop control.
To implement the encoder model on the FPGA fabric, make use of the HDL Coder’s Simulink Library which has over 250 HDL optimized blocks and additionally HDL Code generation is also supported when your model designs are built using Simulink’s library such as Math Operations and other commonly used blocks such as logic, discrete, lookup tables etc.,.
Implementing HDL model designs keep the following in mind:
- The HDL implementation requires all block sample times to be discrete.
- For generating HDL code, create a Design Under Test or (DUT) subsystem which comprises of all the model subsystems which will be implemented on the hardware logic.
- When implementing trigonometric functions, we recommend using Look-Up-Tables (LUTs) as they utilize a single cycle and it’s easier to define the symmetry range from 0 to ½ π
Once the Simulink model is developed partition the model into Hardware and Software atomic subsystems or DUTs. We have now introduced a very fast dynamics into the original model. FPGAs can run in the Megahertz region and balancing the latency is crucial to propagate control signals through the hardware logic. HDL Coder inserts registers which ensure the signals through the parallel paths are coordinated and this process is automated.
To generate hardware efficient HDL Code from Simulink we require the data types to be fixed point. Fixed point data types is used in order to reduce power consumption and hardware resource usage.
For initial prototyping and validation of control algorithm design we can use Floating point data type and generate HDL Code. HDL Coder can generate HDL from native floating-point data type. This capability was awarded the Embedded Award in 2017 for its ability to generate optimal code without sacrificing numerical accuracy.
When the project moves to production, it is strongly recommended that data type be converted to Fixed Point. This data conversion is automated with Fixed Point Designer tool which will gather the range and coverage of the design and recommend Fixed Point data type, keeping the accuracy and maximizing precision. When high-dynamic range calculations are required, making it challenging to efficiently convert it to fixed-point, HDL Code generation supports floating point to generate VHDL or Verilog.
With our partitioned model generate the C Code for the processor using the Embedded Coder.
To generate the HDL Code, use the HDL Workflow Advisor, we will complete series of steps to ensure the HDL block contents are HDL compatible. The Advisor guides you through the stages of generating HDL code for the DUT using a range of tasks. When the HDL Advisor completes its task, you have successfully generated HDL code which is shareable and reusable. The HDL Code Generation report provides details of resources, HW optimizations and provides traceability between the generated code and the Simulink source model.
Prototyping is the natural next step to build confidence on our simulation model. At this stage you have generated the HDL Code for the FPGA Fabric and generated C-Code for the ARM processor using the Embedded Coder and would like to see it work on an actual hardware.
To prototype this implementation, the HDL Code needs to interact with the SoC embedded processor via Advanced eXtensible Interface/AXI bus. This AXI target interface is autogenerated by the HDL Coder, which allows the embedded processor to read and write data from and to the FPGA fabric. Using the HDL Workflow Advisor Set Target Interface, port names and their respective HW interface are populated and generated. The AXI address mapping information is also included in the C header file which is generated by the Embedded Coder. Additionally, you can download Hardware Support Packages for popular boards from Xilinx and Intel which can fully automate the SoC programming.
We have shown you how with no prior FPGA knowledge, you can take advantage of the advanced tools from MathWorks and create the HDL implementations in order to take the fast-computational requirements in your control algorithm onto an SoC device.
Watch Steven Bervoets from Punch Powertrain talk about how they utilized HDL Coder to implement the complex controls for their Switched Reluctance Motor.
To learn more about the HDL Coder and working examples of control applications deployed on SoC visit the HDL Coder product page on the MathWorks Website.
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