Perform simulation and analysis of the SoC architecture of the Xilinx® RFSoC to investigate hardware/software partitioning of the range-Doppler radar algorithm.
In this third video in the series, learn how to develop a Simulink® model that serves as a reference for verifying implementation models.
See how to analyze the algorithm’s memory requirements to determine whether external DDR4 memory is required for hardware implementation. Then learn how to evaluate two candidate hardware/software partitioning alternatives by comparing the effects of performing the FFT operation in the quad-core Arm® Cortex®-A53 processor versus performing the FFT in programmable logic.
Explore how to model the DDR4 memory transactions using Memory Controller and Traffic Generator blocks of SoC Blockset™, and use simulation to determine the latency of memory write and read operations. Pre-characterized models for the Xilinx ZCU111 development board enable accurate evaluation of latency using simulation, without the need for hardware testing.
Then using processor-in-the-loop (PIL) testing, you can perform on-device profiling and measurement of latency for the algorithm running on the processor.
These techniques allow you to determine the latency and implementation complexity of each option so you can decide on an approach that best meets requirements.
In Part 4 of this video series, you will see how SoC Blockset drives the process of generating a complete hardware/software application and deploying it to the ZCU111 development board.
