Capabilities and Features
HDL Verifier™ automates the verification of HDL code on Microsemi® FPGA boards by enabling FPGA-in-the-loop (FIL) simulation. FIL simulation helps ensure that the MATLAB® algorithm or Simulink® design behaves as expected in the real world, increasing confidence in your silicon implementation.
The MATLAB algorithm or Simulink model is used to drive FPGA input stimuli and to analyze the output of the FPGA.
With FIL testing, you can verify your design at FPGA speeds, enabling you to run more extensive sets of test cases and perform regression tests on your design.
When used with HDL Coder, you can use HDL Workflow Advisor to generate the FIL model for Simulink and generate the FPGA programming file for the Microsemi FPGA.
HDL Verifier supports FIL simulation for the following Microsemi FPGA boards:
- Microsemi SmartFusion®2 Advanced Development Kit
- PolarFire® Evaluation Kit
- Microsemi RTG4® Development Kit (RTG-DEV-KIT Rev B)
See Microsemi Usage Requirements for information about supported versions of Microsemi Libero® SoC software.
Platform and Release Support
See the hardware support package system requirements table for current and prior version, release, and platform availability.
View enhancements and bug fixes in release notes.