Bus Assignment

Assign new values to specified bus elements

Libraries:
Simulink / Signal Routing
HDL Coder / Signal Routing

Description

The Bus Assignment block assigns the values of input signals to selected bus elements. Use a Bus Assignment block to change bus element values without adding Bus Selector and Bus Creator blocks that select bus elements and reassemble the elements into a bus. A Bus Assignment block simplifies updating a bus to reflect the processing that occurs in a separate component, such as a subsystem or referenced model.

The Bus Assignment block assigns elements connected to its assignment input ports to specified elements of the bus connected to its bus input port. The block replaces the elements previously assigned to those elements. The change does not affect the composition of the bus; it affects only the values of the elements themselves. Signals not replaced are unaffected by the replacement of other elements.

The elements to which you assign values can be nonbus signals or buses, including arrays of buses. The new values must match the attributes of the elements in the original bus.

By default, Simulink^® repairs broken selections for a Bus Assignment block that are due to upstream bus hierarchy changes. Simulink generates a warning to highlight that it modified the model. To prevent Simulink from making these repairs automatically:

On the Modeling tab of the Simulink Toolstrip, click Model Settings.
Navigate to the Diagnostics > Connectivity pane.
Set the Repair bus selections configuration parameter to Error without repair.

Examples

Assign Signal Values to Bus Elements

Use a Bus Assignment block to replace signals assigned to bus elements.

Open Model

Explore Simulink Bus Capabilities

Work with buses in components, use bus ports at component interfaces, and perform common bus workflows faster.

Open Model

Limitations

The Bus Assignment block does not support messages.
A Bus Assignment block cannot replace a bus in an array of buses. Use an Assignment block instead. For more information, see Assign Values into Arrays of Buses.
A Bus Assignment block cannot replace an element of a bus in an array of buses. To select the index of the bus that you want to modify with the Bus Assignment block, use a Selector block. Then, use that selected bus with the Bus Assignment block.

Ports

Input

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Bus — Input bus with elements to reassign
bus

The input virtual or nonvirtual bus can have elements with real or complex values of any data type supported by Simulink, including bus objects, fixed-point data types, and enumerated data types. The bus can also contain arrays of buses.

:= — New value to assign to bus element
scalar | vector | matrix | array | bus

Each element in the Elements that are being assigned list receives an assignment port. The port label indicates the bus element that corresponds to the port. For an element named signal1, the port label is := signal1.

Connect the signal that you want to assign to the bus element to its corresponding assignment port. The signal connected to the assignment port must have the same structure, data type, and sample time as the corresponding bus element. To change the sample time of one or more elements, use a Rate Transition block. For more information, see Modify Sample Times for Nonvirtual Buses.

Output

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Bus — Output bus
bus

The output virtual or nonvirtual bus includes the assigned bus element values for the selected elements and the unmodified bus element values for the other elements.

Parameters

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Elements in the bus — Elements of input bus
list of element names

This parameter is read-only.

Select elements in the input bus to operate on them.

An arrow next to an element name indicates that an element is a nested bus. To display the elements in a nested bus, click the arrow.

With one or more elements selected, click:

Find — Find the source of the selected elements. Simulink opens and highlights the system containing the element source.
Select — Add the selected elements to the list of elements to be assigned values. For more information, see Elements that are being assigned.

To refresh the list to reflect modifications to the input bus, click Refresh.

Programmatic Use

Block Parameter: InputSignals

Type: cell array | cell array of cell arrays

Values: names of input bus elements

Default: none

Filter by name — Filter for input elements
text

Specify a search term to use for filtering a long list of input elements. Do not enclose the search term in quotation marks. The filter does a partial string search.

To access filtering options, such as using a regular expression for specifying the search term, click the Show filtering options button to the right of the Filter by name box.

Enable regular expression — Option to filter input elements with regular expressions
off (default) | on

Enable the use of MATLAB^® regular expressions for filtering element names. For example, enter t$ in the Filter by name box to display all elements whose names end with a lowercase t and their immediate parents. For more information, see Regular Expressions.

Dependencies

To access this parameter, click the Show filtering options button to the right of the Filter by name box.

Show filtered results as a flat list — Option to display filtered input elements in a flat list
off (default) | on

By default, the list of input elements displays elements in a hierarchical tree. To display filtered elements in a flat list that uses dot notation to reflect the bus hierarchy, select this parameter.

Dependencies

To access this parameter, click the Show filtering options button on the right of the Filter by name box.

Elements that are being assigned — Bus elements to be assigned new values
list of element names

For each element in this list, the block has an assignment port. The port label contains the name of the corresponding element.

To add assignment ports for elements:

Select one or more elements from the Elements in the bus list.
If you select multiple elements from the Elements in the bus list, the order in which you select them sets their order in the Elements that are being assigned list.
Optionally, specify where you want the elements to appear in the Elements that are being assigned list. Select the element below which you want the added elements to appear. If you do not select an element, added elements appear at the end of the list.
Click Select.

To change the order of the assignment ports, select an element or multiple contiguous elements in the list, then click Up or Down. Port connectivity is maintained when you change the element order.

To remove assignment ports, select the corresponding elements in the list, then click Remove.

If an element in the list is not in the input bus, the element name starts with three question marks (???). Modify the input bus to include an element of the specified name or remove the element from the list.

Programmatic Use

Block Parameter: AssignedSignals

Type: character vector | string scalar

Values: comma-separated list of element names

Default: none

Block Characteristics

Data Types	`Boolean` \| `bus` \| `double` \| `enumerated` \| `fixed point` \| `half` \| `integer` \| `single` \| `string`
Direct Feedthrough	`yes`
Multidimensional Signals	`yes`
Variable-Size Signals	`yes`
Zero-Crossing Detection	`no`

Extended Capabilities

C/C++ Code Generation
Generate C and C++ code using Simulink® Coder™.

Actual data type or capability support depends on block implementation.

HDL Code Generation
Generate Verilog and VHDL code for FPGA and ASIC designs using HDL Coder™.

HDL Coder™ provides additional configuration options that affect HDL implementation and synthesized logic.

To learn more about using buses for HDL code generation, see Buses (HDL Coder) and Use Bus Signals to Improve Readability of Model and Generate HDL Code (HDL Coder).

HDL Architecture

This block has one default HDL architecture.

HDL Block Properties

ConstrainedOutputPipeline	Number of registers to place at the outputs by moving existing delays within your design. Distributed pipelining does not redistribute these registers. The default is `0`. For more details, see ConstrainedOutputPipeline (HDL Coder).
InputPipeline	Number of input pipeline stages to insert in the generated code. Distributed pipelining and constrained output pipelining can move these registers. The default is `0`. For more details, see InputPipeline (HDL Coder).
OutputPipeline	Number of output pipeline stages to insert in the generated code. Distributed pipelining and constrained output pipelining can move these registers. The default is `0`. For more details, see OutputPipeline (HDL Coder).

PLC Code Generation
Generate Structured Text code using Simulink® PLC Coder™.

Fixed-Point Conversion
Design and simulate fixed-point systems using Fixed-Point Designer™.

Actual data type or capability support depends on block implementation.

Version History

Introduced before R2006a

Bus Assignment

Description