Signal and Data Type Support

HDL Coder™ supports code generation for Simulink^® signal types and data types with a few special cases.

Buses

If your DUT or other blocks in your model have many input or output signals, you can create bus signals to improve the readability of your model. A bus signal or bus is a composite signal that consists of other signals that are called elements.

You can generate HDL code for designs that use virtual and nonvirtual buses. For example, you can generate code for designs that contain:

DUT subsystem ports connected to buses.
Simulink and Stateflow^® blocks that support buses and HDL code generation.

Supported Blocks with Buses

Bus-capable blocks are blocks that can accept bus signals as input and produce bus signals as outputs. For a list of bus-capable blocks that Simulink supports, see Bus-Capable Blocks. HDL Coder supports code generation for bus-capable blocks in the HDL Coder block library. For more details, see the "HDL Code Generation" section of each block page. The supported blocks include:

In addition, subsystems, models, and these user-defined functions support buses for simulation and HDL code generation:

Subsystem
Model references, see Model Referencing for HDL Code Generation.
Stateflow Chart (Stateflow)
MATLAB Function blocks
MATLAB System blocks
Vision HDL Toolbox™ blocks that accept a pixelcontrol bus for control input

Bus Support Limitations

Buses are not supported in the IP Core Generation workflow. In addition, you cannot generate code for designs that use:

A Black box model reference connected to a bus.
A bus input to a Delay block with nonzero Initial condition.

Enumerations

You can generate code for Simulink, MATLAB^®, or Stateflow enumerations within your design.

Requirements

The enumeration strings must have unique names and must not use a reserved keyword in the Verilog^®, SystemVerilog or VHDL language.
If your target language is Verilog or SystemVerilog, all enumeration member names must be unique within the design.

Restrictions

Enumerations at the top-level DUT ports are not supported with the following workflows or verification methods:

IP Core Generation workflow
Simulink Real-Time FPGA I/O workflow
FPGA-in-the-loop
HDL Cosimulation

Matrices

You can use matrix types with these blocks in your design. For more details, see the "HDL Code Generation" section of each block page.

HDL Coder Block Library	Supported blocks
Discontinuities	These blocks are supported: Dead Zone Relay Saturation
Discrete	These blocks are supported: Delay Discrete-Time Integrator Memory Tapped Delay Unit Delay Unit Delay Enabled Synchronous Unit Delay Enabled Resettable Synchronous Unit Delay Resettable Synchronous Zero-Order Hold
HDL Floating Point Operations	The Rounding Function block is supported.
HDL Operations	All blocks in this library are supported.
HDL RAMs	Blocks in this library are not supported.
HDL Subsystems	Blocks in this library are not supported.
Logic and Bit Operations	These blocks are supported: Bit Clear Bit Concat Bit Reduce Bit Rotate Bit Set Bit Shift Bit Slice Extract Bits Logical Operator Relational Operator Shift Arithmetic
Lookup Tables	Blocks in this library are not supported.
Math Operations	These blocks are supported: Abs Sum Assignment Bias Complex to Real-Imag Gain Product, Matrix Multiply Matrix Concatenate Math Function Real-Imag to Complex Reshape Sign Sum Unary Minus Increment Stored Integer Increment Real World Decrement Stored Integer Decrement Real World Sum Product of Elements
Model Verification	All blocks in this library are supported.
Model-Wide Utilities	The DocBlock is supported. The Model Info block does not support matrix data types.
Ports & Subsystems	The Subsystem block is supported.
Signal Attributes	These blocks are supported: Data Type Conversion Data Type Duplicate Probe Rate Transition Signal Conversion Signal Specification
Signal Routing	These blocks are supported: Mux Multiport Switch Selector Bus Assignment Bus Creator Bus Selector In Bus Element Out Bus Element
Sources	These blocks are supported: Constant Enumerated Constant Inport
Sinks	These blocks are supported: Display Outport Scope To Workspace To File
User-Defined Functions	The MATLAB Function block is supported.

Unsupported Signal and Data Types

Arrays stored in row-major layout are not supported for HDL code generation
Variable-size signals are not supported for code generation.
The Dataset objects set to timetable are not supported for HDL code generation. For more information, see Dataset signal format

Related Examples

Generating HDL Code for Subsystems with Array of Buses