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Design and Simulate SerDes Systems

Design and simulate SerDes systems using the SerDes Designer app

High-speed electronic systems suffer from signal degradation caused by various impairments such as impedance mismatch, attenuation, and crosstalk. Using the equalization and gain modulation blocks in the SerDes Toolbox™, you can compensate for the distortions introduced by the lossy channels.

Starting with the SerDes Designer app, you can design the top-level SerDes systems and perform statistical analysis. Use the building blocks and system objects to design, configure, simulate and analyze the SerDes system including the transmitter and the receiver.


SerDes DesignerDesign and analyze SerDes systems for export to Simulink, MATLAB and IBIS-AMI
S-Parameter FitterConvert S-Parameter network to impulse response
CTLE FitterFit poles and zeros to CTLE transfer functions


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DFECDRDecision feedback equalizer (DFE) with clock and data recovery (CDR)
CDRModels a clock data recovery circuit
FFEModels a feed-forward equalizer
CTLEModels continuous time linear equalizer (CTLE)
AGCAutomatically adjusts gain to maintain output waveform amplitude
VGAModels a variable gain amplifier
SaturatingAmplifierModels a saturation amplifier
IBIS-AMI clock_timesRecover SerDes clock time values from custom DFECDR and CDR
PassThroughPropagates baseband signal without modification
Analog ChannelConstruct loss model from channel loss metric or impulse response
ConfigurationConfigure system wide settings in SerDes system model
Eye Diagram ScopeDisplay eye diagram of time-domain signal
StimulusSet waveform generation method and number of symbols to simulate in SerDes model


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serdes.DFECDRDecision feedback equalizer (DFE) with clock and data recovery (CDR)
serdes.DFEMinimize intersymbol interference (ISI) at clock sampling times
serdes.CDRPerforms clock data recovery function
serdes.FFEModels a feed-forward equalizer
serdes.CTLEContinuous time linear equalizer (CTLE) or peaking filter
serdes.AGCAutomatically adjusts gain to maintain output waveform amplitude
serdes.VGAModels a variable gain amplifier
serdes.SaturatingAmplifierModels a saturating amplifier
serdes.PassThroughPropagates baseband signal without modification
serdes.ChannelLossCreate simple lossy transmission line model
serdes.StimulusSet a pseudorandom binary sequence (PRBS) pattern and number of symbols to simulate in SerDes model
SParameterChannelConvert S-parameter to impulse response


optPulseMetricPulse response metric for optimization routines
prbsPseudorandom binary sequence
impulse2stepStep response from impulse response
impulse2pulsePulse response from impulse response
step2impulseImpulse response from step response
pulse2impulseImpulse response from pulse response
pulse2stateyeStatistical eye from pulse response
pulse2pdaPeak distortion analysis eye from pulse response
pulse2waveData pattern waveform from pulse response
wave2pulsePulse response from data pattern waveform