Get Started with Simulink Design Verifier
Simulink® Design Verifier™ uses formal methods to identify hidden design errors in models. It detects blocks in the model that result in integer overflow, dead logic, array access violations, and division by zero. It can formally verify that the design meets functional requirements. For each design error or requirements violation, it generates a simulation test case for debugging.
Simulink Design Verifier generates test cases for model coverage and custom objectives to extend existing requirements-based test cases. These test cases drive your model to satisfy condition, decision, modified condition/decision (MCDC), and custom coverage objectives. In addition to coverage objectives, you can specify custom test objectives to automatically generate requirements-based test cases.
- About Systematic Model Verification Using Simulink Design Verifier
Overview of features and capabilities of Simulink Design Verifier to help you get started with formal verification.
- Overview of the Simulink Design Verifier Workflow
Overview of the basic Simulink Design Verifier workflow.
- Detect Design Errors in Controller Model
Identify hidden design errors in your model by using design error detection analysis.
- Generate Test Cases for a Simplified Cruise Control Model
Analyze a simple control system model that demonstrates Simulink Design Verifier capabilities.
What Is Simulink
Introduction to Simulink Design Verifier.
Requirements and Advanced Model Checks Workflow
Manage requirements in Simulink, perform advanced model checks, and check your model for run-time errors.
Requirements-Based Testing Workflow
Explains how to create a test using a test sequence, define a formal assessment, link test cases to requirements, run test suites, and analyze missing model test coverage.